PDP11 PeripheralsHbk 1972 - Trailing-Edge
PDP11 PeripheralsHbk 1972 - Trailing-Edge
PDP11 PeripheralsHbk 1972 - Trailing-Edge
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BIT<br />
*15<br />
14<br />
13<br />
*12<br />
*11<br />
* 10<br />
9<br />
NAME<br />
Time Out (TO)<br />
AC LO<br />
Not Neutral (NN)<br />
COM2<br />
COM1<br />
IE2<br />
Reset<br />
OESCRI PTION<br />
This bit, when set, means that the timer<br />
timing out caused the last position<br />
change. Therefore, if CON (bit 7) and TO<br />
(bit 15) are both set, it means that the<br />
processor gained control because of a<br />
timeout. if only TO is set it means that the<br />
processor lost control because of a time·<br />
out. I n the case of a processor that loses a<br />
switch because of a timeout but then reo<br />
requests it and gets the switch back im·<br />
mediately, the TO bits in both control registers<br />
will be set.<br />
This bit is cleared by writing into either<br />
byte of the control register, a power up or<br />
down, RESET, or START. This bit is read·<br />
only.<br />
This bit is the same as AC LOon the<br />
switched bus. AC LO is the warning signal<br />
to the processor that causes the power fail<br />
trap. This bit is read only.<br />
This bit is set whenever the switch is not in<br />
the NEUTRAL position. This bit is read<br />
only.<br />
This bit is set by the other processor set·<br />
ting its COM1 (bit 11). If IE2 (bit 10) is set<br />
when COM2 becomes set, an interrupt will<br />
occur. This bit is read only, and is always<br />
the same as the other processor's COMl.<br />
When this bit is set, COM2 (bi'l: 12) of the<br />
other processor's control register is set<br />
causing an interrupt on its bus if its 1£2<br />
(bit 10) is set. This bit is cleared by a<br />
power up or down, RESET, or START.<br />
This bit allows the other processor to<br />
cause an interrupt. Setting this bit when<br />
bit 12 is set causes an interrupt. Another<br />
interrupt does not occur until either IE2<br />
(bit 10) or COM2 (bit 12) gets cleared and<br />
then sets again. This bit is cleared by a<br />
power up or down, RESET or START.<br />
Setting of this bit causes a 10!1S In·<br />
itialize signal on the switched bus if the<br />
switch is in the connected or controlled<br />
positions on this side. This bit remains set<br />
for as long as the initialize signal is on the<br />
switched bus. Whenever this bit is set by<br />
the program, a loop should be executed<br />
that guarantees the bit is off before any<br />
references are made to the switced bus. If<br />
105
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