PDP11 PeripheralsHbk 1972 - Trailing-Edge
PDP11 PeripheralsHbk 1972 - Trailing-Edge
PDP11 PeripheralsHbk 1972 - Trailing-Edge
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
1.2.2 Interrupt Structure<br />
If the appropriate interrupt enable bit is set, in the control and status register of a<br />
device, transition from 0 to 1 of the READY or ERROR bit causes an interrupt<br />
request to be issued to the processor. Also if READY or ERROR is a 1 when the interrupt<br />
enable is turned on, an interrupt request is made. If the device makes the<br />
request at a priority greater than that at which the processor is running and no<br />
other conflicts exist, the request is granted and the interrupt sequence takes<br />
place:<br />
a. the current program counter (PC) and processor status CPS) are pushed onto<br />
the processor stack;<br />
b. the new PC and PS are loaded from a pair of locations (the interrupt vector) in<br />
addressed memory, unique to the interrupting device.<br />
Since each device has a unique interrupt vector which dispatches control to the<br />
appropriate interrupt handling routine immediately, no device polling is required.<br />
Furthermore, since the PS contains the processor priority, the priority at which an<br />
interrupt request is serviced can be set under program control and is independent<br />
of the priority of the interrupt request. The Return from Interrupt Instruction<br />
CRT!) is used to reverse the action of the interrupt sequence. The top two words<br />
on the stack are popped into the PC and PS, returning control to the interrupted<br />
sequence.<br />
1.2.3 Programming Example<br />
A paper tape reader interrupt service could appear as follows:<br />
First the user must initialize the service routine by specifying an address pointer<br />
and a word count<br />
INIT: MOV # BUFADR,POINTER ;set address pointer<br />
MOV #COUNT,COUNTR<br />
MOV # 101,PRS<br />
;set counter<br />
;enable reader program continues until interrupt<br />
When the interrupt occurs and is acknowledged, the processor stores the current<br />
PC and PS on the stack. Next it goes to the interrupt vector and picks up the new<br />
PC and PS beginning at location 70. When the program was loaded the address of<br />
PRSER would be put in location 70 and 200& in 72 (to set priority at 4). The next<br />
instruction executed is the first instruction of the device service routine at PRSER.<br />
PRSER: TST PRS<br />
DONE: RT[<br />
BMIERROR<br />
MOVB PRB,@POINTR<br />
INC POINTR<br />
DEC COUNTR<br />
BEQ DONE<br />
INC PRS<br />
;test for error<br />
;branen if bit 15 set<br />
;move character to buffer<br />
;increment pointer<br />
;decrement character count<br />
;branch when input dOne<br />
;start reader for next character<br />
;retum to interrupt program<br />
4