PDP11 PeripheralsHbk 1972 - Trailing-Edge

The storage element on the M795 is not an edge-triggered device; data must be
established and held for the duration of the loading pulse. Refer to section 2.2.4.4
for circuit implementation details.
The SA register can be incremented by either 1 or 2 as a function of a control input
(+ 3V = + 1; ground = + 2). This incrementation capability allows addressing
of either sequential bytes or words. The register is incremented on the trailing
edge of a positive pulse applied to the count input of the register. The carry between
bits 03 and 04 is broken and brought out to pins on the module. Normally,
these pins are jumpered together externally to allow for a full 16-bit count. However,
they can be controlled to inhibit the carry and to force repeated addressing
of 16 sequential byte addresses. This feature can be used in device-to-device
transfers. An overflow pulse is provided as an output whenever the register is incremented
from all Is to all Os.
The WC register is incremented by either 1 or 2 as a function of its control input.
The register increments on the trailing edge of a positive pulse applied to the
count input of the register. An overflow pulse is also available. Both registers are
reset to aliOs whenever the CLEAR signal is asserted.
Table 2-5 M795 Input Signals
Assertion No. of
Signal Name Level Signals Loading Operation
DIN +3V=1 16 1.5 Data inputs to register.
lOADWC OV 4 Loads data on input into
LOADWC+l selected byte of register.
LOAD SA Low pulse of 250 ns
LOADBA+l minimum duration
WCTO D BUS OV 3 2 Gates selected register
BA TO D BUS to bus.
SA TO A BUS
CLEARWC + BA +3 2 Clears a/l bits. High level
of 1 J.LS minimum duration.
SA I NC CONTROL +3V = + 1 2 3 Controls amount of
WC INC CONTROL OV= +2 incrementation.
COUNTWC +3V 2 4 Trailing edge of positive
COUNT SA pulse increments register
(100 ns minimum).
BA CARRY IN OV 3 Carry into upper bits
of BA.
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