PDP11 PeripheralsHbk 1972 - Trailing-Edge

3.S.3 Interface Programming
To type a character on the secondary UNIBUS system Teletype, the processor on
the primary UNIBUS executes the following sequence of instructions:
MOV '75,UUCSR WHERE: UUCSR IS THE CONTROL REGISTER IN THE INTERFACE
MOV CHAR,XPB CHAR IS THE LOCATION CONTAINING THE CHARACTER
XPB HAS THE VALUE 157566
The address transmitted on the secondary UNIBUS is the 13 least significant bits
of XPB (17566) with the contents of the field select register appended as the 5
most significant bits. The address is therefore 777566, which is the address of the
system Teletype TPB.
A block of data is transferred to locations on the secondary UNIBUS by setting
the hold bit when the field register is set:
MOV FIELD,UUCSR \'lHERE: FI ELD I S THE NUMBER OF THE 4K FI ELD
OF ',WRD ADDRESSES TO BE ACCESSED ON
THE SECONDARY UNIBUS (WITH A 1 APPENDED
TO SET THE HOLD BIT>
Data transfers then access locations in that address field when the address on
the primary UNIBUS has A< 17:13> equal to 00110 and A< 12:00> equal to the
desired value of A< 12:00> on the secondary UNIBUS. If FIELD has the value
11 8 , the address 140020 8 is translated to the address 100020 8 ,
3.9 MEMORY INCREMENT INTERFACE
An Increment Memory interface is used to increment a device-selected memory location
without requiring processor intervention. The interface operates by performing
a DATIP, DATO sequence with the selected memory location. This sequence
is the same as processor operation with a destination operand. Data read
from the memory location by the DATIP transfer is loaded into a counter register.
A count cycle is initiated, and the count is allowed to ripple through the register.
The new value is written back into the memory during the DATa cycle.
A more flexible implementation uses an adder instead of a counter. The contents
of the memory location are brought into a latch, which forms one input to the adder.
The other input can be under device or program control; or a simple increment
operation can be executed by providing a carry into the least significant
bit. The adder permits arbitrary values to be added to the selected location. This
expanded interface is not described in subsequent discussions.
This interface differs from previous interface examples because the device output
is used as a bus address rather than as data. The operations performed on the
data in these locations effectively generate a time-interval histogram directly in
core memory.
3.9.1 Interface Description and Operation
In Figure 3-16, the analog-to digital converter (ADC), which is an external device
that supplies the digital value used as an address, is not part of the interface. One
device register is used in the interface. The device register contains the enable bit
which controls access of the interface to the UNIBUS, and contains the five field
select bits used to select a 4K word block of bus addresses that the interface uses
for conducting transfers. The counter and transmitters are under interface control.
The interface provides all timing and control signals for one cycle of oper-
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