PDP11 PeripheralsHbk 1972 - Trailing-Edge

6.2.2 Interrupt
During an interrupt, the interrupt monitor bit is at 1 (it had become a 1 either during
the same line time clock transition that caused the interrupt, or during a previous
transition.
Shown below is a program using the LKS in the interrupt mode. Its purpose is to
enter the routine TIME after every N interrupts. When the main program is interrupted,
it is directed to the vector address LKV which is 100, and then to LKV + 2
which is 102. The word in 100 is the adddress of the first instruction in the interrupt
routine, and is consequently transferred into the processors program
counter. The word in 102 is the new status register. The new status word contains
the number 300 which indicates a priority level BR6 with all five condition codes,
T, Z, N, V, and C equal to O.
LKS 777546
LKV 100
MAIN: MaV # N, CNTR
MaV # 100, LKS
LKV: LK SERV
300
LKSERV: DEC CNTR
BEQ TIME
RTI
TIME MaV # N, CNTR
RTI
ENB INTR
6.2.3 Non Interrupt
The LKS may be used in the non·interrupt mode as well as in the interrupt mode.
Shown below is a routine using the LKS in the non·interrupt mode. The program
is designed to alternate between two program routines, each lasting for appro·
ximately the time periods between line clock changes which are either 16.67 or 20
ms. Each routine contains a program loop which lasts for a considerably shorter
time duration than the period between line clock changes.
LKS = 777546
START: CLRB LKS
SYNC: TSTB LKS
BPL SYNC
CLRB LKS
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