PDP11 PeripheralsHbk 1972 - Trailing-Edge

only for use with the DC08CS distribution panel. The DCOBCS Telegraph dis·
tribution panel will not accommodate any of the DMllDA, 8, or C line interface
modules.
8.5.2 Operation
A. User View
1. Status and Control Registers.
Each DMll contains four 16 bit registers. One register contains command and
status information about the DM11 (e.g. receiver enable, full or half duplex select,
etc.) Another register, the BUFFER Active Register (BAR), contains one bit per
line. Setting a bit in the BAR initiates transmission on the associated line. The bit
is cleared by the hardware when transmission is complete. A third register, the
Break Control Register (BCR), contains one bit per line. Setting a bit will force
that line's output to a space, causing a break condition. Clearing the bit returns
the appropriate line to a normal condition (mark if the transmitter is inactive).
The final register is the Base Address Register (BAOR). It selects the base address
of the four core tables associated with each OM 11. The base address is settable to
even 400 (octal) word boundaries.
2. Software Tables.
Four tables are required to be set up in the software. The base address of these
tables is set by writing into the Base Address Register in the OMll. The four tao
bles are contiguous, and require 128 (decimal) words of core, beginning on an
even 400 (octal) word boundary. T .... IO tables are required for transmit, and two for
receive. The format is as follows:
Where X is the contents of the Base Address Register
X is the address of the Current Address Table (CAT· 16 decimal words)
X + 20 (octal) is the Word Count Table (WCT . 16 decimal words)
X +40 (octal) is the Bit Assembly Table (BAT· 16 decimal words)
X + 100 (octal) is the Circular Buffer (CB . 64 decimal words)
Figure 8·4 shows a core map of these tables, and their word formats.
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