PDP11 PeripheralsHbk 1972 - Trailing-Edge

a. If immediate interrupt operation is to be initiated, a device which has been se·
lected as bus master asserts INTR and a vector address on the D lines, at the
same time that it clears SACK and asserts BBSY. If data transfers occur prior
to interrupt then SACK must remain asserted until INTR is asserted. If the de·
vice has been making data transfers prior to the interrupt, it should assert
SACK through the last cycle.
b. The processor receives the INTR signal, waits 75 ns for deskew to ensure that
a/l bits of the interrupt vector address are available, and asserts SSYN when
the data is read in. :
c. The bus master (interrupting device) receives SSYN and clears INTR, the D
lines, and BBSY. This constitutes active release of the bus to the processor.
d. The processor clears SSYN when INTR is cleared, and enters the interrupt se·
quence to store the contents of the current PC and PS registers and replace
them with the contents of the location specified by the vector address.
1.3.3 Priority Chaining
The PDp-ll uses electrical chaining of devices to assign minor priority levels.
These levels separate devices of the same major priority level to provide a full ar·
ray of priority servicing. Figure 1-8 illustrates the mode of operation and advan·
tages of this system. Six devices are shown in order of their electrical distance
from the processor. Three devices are at major priority level 4: device A, device C,
and device D. The remaining three are at major priority level 5.
f-BR5
f-BR4
r-BG5
PROCESSOR -BG4 -
DEVICE
A
LEVEL 4
-
DEVICE DEVICE DEVICE DEVICE
B C D E
LEVEL 5 LEVEL 4 LEVEL4 LEVEL 5
Figure 1-8 Priority Chaining Example
-
DEVICE
F
LEVEL 5
-
TO NEXT
DEVICE
If the processor is at priority level 5 or above, no bus requests are granted from
any of these devices. At a processor priority of 4, only requests from devices B, E,
or F are granted. Assume that the processor priority is 2 and also that during one
instruction cycle, devices C, E, and F assert bus requests. At the end of the in·
struction, the processor conducts a PTR operation. Since BR 5 is asserted, the
processor does not respond to BR 4 (device C). When BG 5 is asserted, the signal
first goes to device B. After a delay to clock the interrupt control shift register
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