PDP11 PeripheralsHbk 1972 - Trailing-Edge
PDP11 PeripheralsHbk 1972 - Trailing-Edge
PDP11 PeripheralsHbk 1972 - Trailing-Edge
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Second, the DRDB functions as a 16·bit read only register. Information to be read<br />
is provided by the user device on the DATA IN signal lines. These lines are not<br />
buffered and must be held until either read under program control or transferred<br />
directly to memory (DATO bus cycle).<br />
Address and Vector Assignments<br />
Direct bus access level: NPR (hardwired)<br />
Priority interrupt level: BR5 (hardwired)<br />
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