PDP11 PeripheralsHbk 1972 - Trailing-Edge

nanoseconds for the DM 11)
UN IBUS Time Used Per Character
(8 bits of data plus 1 stop bit)
DM11 Bit Service Time
(One Latency plus 2 Memory Cycles)
2.2 microseconds
17.1 microseconds
5.7 microseconds
In the DM11 the critical timing is 117 of a bit time since all lines are sampled at
seven times the baud rate. In the worst case all lines must be serviced in 117 of a
bit time to avoid violating the distortion speCification. Therefore the number of
lines that the DM11 can handle is a function of tAe Baud rate. The number of
lines as a function of the baud rate are:
Baud Rate 117 of a Number of Number of
Bit Time Full Duplex Half Duplex
(Microseconds) Lines Lines
1200 119 16 20
600 238 32 40
300 476 64 80
150 952 128 160
110 1298 160 216
75 1904 256 320
50 2857 420 527
The maximum percentage of UNIBUS Time used by the DM11 is different for full
or half duplex operation, but independent of the Baud rate. (Note that MM11·F
memory is required for 1200 Baud operation).
Assume Baud rate equal 1200; therefore the bit time is 833,..s. For half duplex op·
eration, a DM11 can service 20 lines and at 1.9 p.s per service requires 38.0p.s per
bit time or 4.6% of the UNIBUS time. For full duplex operation, a DM11 can ser·
vice 16 lines and a 1.9p.s per service for receive and transmit requires 60.8,..s per
bit time or 7.3% of the UNIBUS time.
Note that the maximum Baud rate for the DM 11 is 1200 Baud. It will not service a
smaller number of lines at a higher Baud rate.
S.5.3 Programming
a. Data Selection
Each DM11·AA, DMll·AB or DMll·AC multiplexer contains four registers and
hence, requires four addresses. Address space has been assigned for 16 DM 11
mu Iti plexers.
The four registers and their address are listed below for DM11A Unit xx, where xx
ranges from 00 to 17.
REGISTER
Status Register
Buffer Active Register
Break Status Register
Base Address Register
ADDRESS
175xxO
175xx2
175xx4
175xx6
Each DMll·M, DMll·AB or DMll·AC requires two interrupt vectors; one for the
receiver and one for output done and error. The vector addresses are assigned
from 300 to 777. The DMll·A follows the KL11s, the DClls and the DP11s in
contiguous vector address assignments from 300 (i.e. the DM ll·A's first vector
address starts where the KL11, DCll, and DPll leave off. If there are no KL11's
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