PDP11 PeripheralsHbk 1972 - Trailing-Edge

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TIME (ns) o 150 225 300 375 450 525 MASTER WA ITS 75ns THEN STROBES DATA AND CLEARS MSYN MASTER WAITS 75ns THEN CLEARS ADRS 8 CONTROL COMPLETE NOTES' Worst case propagation delay of 75ns shown. Total time= 525ns for a single transfer. Next cycle may begin at 450ns when master may assert new address and control. Maximum sustained transfer rate is 2.2 million words/second. SLAIi'E CLEARS SSYN a DATA Figure 1-11 Typical DATI Timing Flow 195
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CONTENTS PART I Chapter 1· Program
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viii
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Chapter 8 - COMMUNICATIONS OPTIONS
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6 5-4 3-1 o Interrupt Enable Memory
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PART I Chapter 2 Basic I/O Terminal
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2.2.3 Programming Examples Reading
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Model Type Power Descri ption L T33
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Punch Interrupt Service This interr
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LPII HIGH SPEED LINE PRINTER 19
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BIT 15 14 13 12 11 10 9 8 7 6 NAME
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LA30-DECwriter 29
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Ribbon: Code: Temperature: Humidity
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Figure 3"2 - DECtape Block Arrangem
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3-1 Function Bits o DO' Word Count
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Density: Data Capacity: Tape Motion
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TU 10 MAGTAPE UNIT 3.2.2 Operation
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10 End of Tape (EaT) 9 Record Lengt
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When the MTBRC is used in a space f
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4.2 STORAGE DISPLAY VTOIA The VT01A
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Brightness: Linearity: Deflection M
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Weight: Heat Dissipation: Operating
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PART I Chapter 5 Disk Storage Devic
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BIT 15 14 13 12 11 10 9 8 7 NAME Sp
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RFll/RSll DECDISK 74
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7 Data Request Late (DRL) 6 Unused
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(A stepdown autotransformer is prov
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BIT 15 14 13 12 11 10 9 8 7 NAME Dr
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15-13 Drive Select (DR SEL) Contain
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PART I Chapter 6 Clocks 6.1 PROGRAM
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Count Set Buffer Register (Write On
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ON: TST8 LKS 8PLON CLR8 LKS OFF: TS
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The signal on the UNIBUS that cause
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The internal timer is started every
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7.2.9 Specifications Bus Address: P
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PART I Chapter 8 Communications Opt
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10,9 Character Length 8 Superv. Tra
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8.2.5 Ordering Information DEC. NO.
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used by the ACU. It allows the prog
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Physical Connection: Power Required
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Pin 1 2 3 4 5 6 7 8 15 17 20 22 24
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10 Clear to Send 9 Request to Send
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DPll-KA DPll H312A DP11-DA Internal
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3. Receive Procedure. The programmm
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nanoseconds for the DM 11) UN IBUS
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2 Request to Send Data terminal Rea
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B. Private line Modems (No Control)
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8.6 FULL DUPLEX 8·BIT ASYNCHRONOUS
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Each multiplexer channel switch con
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c. Output Driver Module BW403 . Is
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Page 362: 172
Page 366: 174
Page 372: Transfer Request Handling The reque
Page 376: PART II Chapter 1 UNIBUS Theory and
Page 382: . Bus Grant Lines (BG
Page 392: f. When the selected slave sees its
Page 400: (discussed in Paragraph 2.3.5), the
Page 404: 475 COMPLETE NOTES' Worst ease prop
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Page 428: +5V TYPICAL UNIBUS DRIVER +5V TYPIC
Page 432: Figure 2-4 UNIBUS Jumper Module M92
Page 448: Table 2-3 Gating Control Signals Mo
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Figure 2-17 State Diagram of Master
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2.2.6 M795 Word Count and Bus· Add
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Table 2·6 M795 Output Signals Asse
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Signal Name BUS C ADRS TO BUS ADRS
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2.4 PDP·ll INTERFACE HARDWARE The
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2.4.2.5 External Device Cables-An e
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Signal levels used in the interface
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3.3.2 DRll-A Implementation A conve
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I\) O'l o READY (1) H START CONVERS
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nel and low COY) for a transfer fro
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5 through 1 of the UNIBUS-to-UNIBUS
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ation and each successive cycle of
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Second, the DRDB functions as a 16
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260 264 270 USER RESERVED 274 USER
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777410 RKBA 777406 RKWC 777404 RKCS
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772546 772544 772542 772540 772536
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770070 LATENCY TESTER 770056 TO 770
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TABLE B-2 UNIBUS PIN ASSIGNMENTS (B
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292
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RS64 Disk .........................
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