PDP11 PeripheralsHbk 1972 - Trailing-Edge

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Chapter 8 - COMMUNICATIONS OPTIONS .................................... "" ................ 109 ASYNCHRONOUS LINE INTERFACE, DCll ............................................ 109 AUTOMATIC CALLING UNIT INTERFACE, DNll .................................... 116 SYNCHRONOUS INTERFACE, DPll ....................................................... 122 ASYNCHRONOUS 16·LlNE SINGLE SPEED MULTIPLEXER, DMll .......................................... 131 FULL DUPLEX 8-BIT ASYNCHRONOUS : LINE INTERFACE, KLll.. .................................... 151 ASYNCHRONOUS NULL MODEM, H312A ............................................... 152 Chapter 9 - DATA ACQUISTION AND CONTROL OPTIONS ................................ 153 LOW LEVEL ANALOG INPUT SUBSYSTEM, AFCll ................................. 153 ANALOG TO DIGITAL CONVERSION SUBSYSTEM, ADOID ............................................ 158 DIGITAL TO ANALOG CONVERSION SUBSYSTEM,AAIID ............................................. 161 UNIVERSAL DIGITAL CONTROL SUBSYSTEM, UDCll.. .................................... 163 x
Page 4: CONTENTS PART I Chapter 1· Program
Page 14: viii
Page 20: PART I Chapter 1 Programming Periph
Page 26: 1.2.2 Interrupt Structure If the ap
Page 30: ASR 33 TELETYPE performed at rates
Page 38: RDRINT: MOVS TKS,(Rl) + ;Put charac
Page 48: RDRI NT: TST PRS ;TEST FOR ERROR OU
Page 54: PC 11 CONTROL Consists of: INTERRUP
Page 66: CM 11 MARK SENSE CARD READER CRll P
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Data from one column at a time of t
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Printer Buffer (PRB) BIT 15-7 6-0 1
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PART I Chapter 3 Magnetic Tape Opti
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ation repeated. Indicates that the
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ERROR: LOOP3: BGT FORWRD BLT SEARCH
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Humidity: Input Power: TC11 Power:
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In error conditions 1 through 3, th
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5 Beginning Of Tape (BOT) 4 Seven C
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PART I Chapter 4 Display Terminals
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4.4 POINT PLOT DISPLAY VR14 The VR1
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4.5.1 Specifications Screen Size: C
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DEC-links usage may be defined enti
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Real-time look ahead is provided by
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Average Access Time: Maximum Access
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BIT NAME 15 Error (ERR) 14 Freeze (
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5.3.5 Specifications Disks: Tracks:
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DECPACK DISK CARTRIDGE SYSTEM 82
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11 Inhibit Inc. (INH SA) Setting th
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those functions. such as CONTROL RE
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BIT 15 NAME Error 14-8 Unused 7 Don
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6.2.2 Interrupt During an interrupt
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The switches do not allow two proce
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7.2.3 Fail-Soft Operation The bus s
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BIT *15 14 13 *12 *11 * 10 9 NAME T
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108
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ety of asynchronous terminals or to
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Receiver Buffer Register (RBUF) Tra
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A Detect Answer option is used. The
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tain an interrupt. It is cleared by
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2. Sync characters will be treated
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10-8 Bits Per Character 7 Receive D
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Modem Compatibility (Typical) Type
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only for use with the DC08CS distri
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memory used. For the MM'l1-F 950 na
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5-4 Memory Extension 3 Not Used 2 M
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Control Signals: Physical: Environm
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D. Telegraph Line Interfaces DEC NO
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PART I Chapter 9 Data Acquisition a
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9.3.3 Specifcations For D/ A Conver
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9.4.7 Specifications Modes of Opera
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2 UNIBUS AND INTERFACING 171
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PART II Introduction ..............
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PART II INTRODUCTION This section d
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Interrupt Requests Devices that gai
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Lines A specify a unique 16-bit wor
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a. Master sets C =00 for DATI or C=
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a. If immediate interrupt operation
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The bus master places address, cont
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TIME (ns) o 150 225 300 375 450 525
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200
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+5V TYPICAL UNIBUS DRIVER +5V TYPIC
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Figure 2-4 UNIBUS Jumper Module M92
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Table 2-3 Gating Control Signals Mo
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Figure 2-17 State Diagram of Master
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2.2.6 M795 Word Count and Bus· Add
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Table 2·6 M795 Output Signals Asse
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Signal Name BUS C ADRS TO BUS ADRS
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2.4 PDP·ll INTERFACE HARDWARE The
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2.4.2.5 External Device Cables-An e
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Signal levels used in the interface
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3.3.2 DRll-A Implementation A conve
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I\) O'l o READY (1) H START CONVERS
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nel and low COY) for a transfer fro
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5 through 1 of the UNIBUS-to-UNIBUS
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ation and each successive cycle of
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Second, the DRDB functions as a 16
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260 264 270 USER RESERVED 274 USER
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777410 RKBA 777406 RKWC 777404 RKCS
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772546 772544 772542 772540 772536
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770070 LATENCY TESTER 770056 TO 770
Page 598:
TABLE B-2 UNIBUS PIN ASSIGNMENTS (B
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292
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RS64 Disk .........................
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