PDP11 PeripheralsHbk 1972 - Trailing-Edge

PART II
INTRODUCTION
This section describes detailed operation of the UNIBUS and methods for interfacing
to the UNIBUS for the addition of custom-designed peripheral equipment
to the PDP-ll System. It is assumed that the reader is familiar with the PDP-ll
System and has a thorough understanding of the principles and concepts introduced
in the PDP-II Processor Handbook ..
The following documents used in conjunction with this Handbook will help the
reader understand interface techniques and the overall PDP-ll System:
a. PDP-ll Processor Handbook
b. Processor Manual
c. Digital Logic Handbook
All communication between PDP-ll system components is accomplished by a
single high-speed bus called the UNIBUS. Four concepts are extremely important
for an understanding of the hardware and software implications of the UNIBUS.
Each concept is covered separately in subsequent paragraphs.
Single Bus
The UNIBUS is a single, common path that connects the processor, memory, and
all peripherals. Addresses, data, and control information are transmitted along
the 56 lines of the bus. Figure 1 is a simplified block diagram of the PDP-ll System
and UNIBUS.
UN I BUS
Figure 1 PDP-II System Simplified Block Diagram
The form of communication is the same for every device on the UNIBUS. The pro·
cessor uses the same set of signals to communicate with memory and peripheral
devices. Peripheral devices also use this set of signals when communicating with
the processor, memory, or other peripheral divices.
All instructions applied to data in memory can be applied equally well to data in
peripheral device registers. Therefore, peripheral device registers may be manipu,
lated as flexibly as memory by the processor. This is an especially powerful fea·
ture, considering the special capability of PDp·ll instructions to process data in
any memory location as though it were an accumulator.
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