PDP11 PeripheralsHbk 1972 - Trailing-Edge

f. When the selected slave sees its address and MSYN, and it is ready to accept
the data present on the D lines (slave may be busy completing a previous in·
ternal operation), it strobes in the data and asserts SSYN.
NOTE
Data on the D lines is guaranteed valid for 75ns minimum
after SSYN is asserted. Data is not guaranteed
valid when the slave receives negated MSYN. The pro·
cessor times out and removes MSYN if no SSYN reo
sponse is made within 25fLsec.
g. The master receives SSYN and negates MSYN.
h. After 75 ns minimum wait, the master removes or alters the A, C, and D lines.
If another DATO or DATOB follows, then the master repeats the above se· F
quence starting at step b. If this is last bus cycle of the master operation and
when A, C, and D lines are all clear, then the master clears BBSY and relin·
quishes bus control. If an input operation follows, the next cycle starts at step
a of the DATI or DATIP operation.
i. The slave sees the negation of MSYN and negates SSYN.
1.3 PRIORITY TRANSFER TRANSACTIONS
Transfer of bus control from one device to another is determined by priority arbitration
logic, which is part of the processor. Requests for the bus can be made at
any time (asynchronously) on the bus request (BR) and non-processor request
(NPR) lines. During each bus cycle, the arbitration logic first checks for an NPR
request (since these requests take precedence over processor use of the bus). If
an NPR is present, the logic issues an NPG Signal and receives a selection ack·
nowledge (SACK) signal in return. This procedure occurs simultaneously with the
current data transfer. When the device scheduled to become the new bus master
is selected, it waits for the present master to clear bus busy (BBSY); then, the
newly selected device becomes bus master and asserts BBSY.
A similar procedure occurs at the end of each instruction when the priority arbitration
logic checks the bus request lines against the processor priority (as determined
by bits of the processor status register) and the priority logic issues
a grant on the corresponding line. Thus, one of the four levels of BR
requests is granted by the processor between instructions unless the instruction
currently being executed causes an internal trap (either an error or trap instruction).
In this case, BR requests are not granted until completion of the first instruction
following the trap sequence. The highest request is always granted first
(if the processor priority level is lower than the request level). The grant signals always
pass serially through each device connected to the corresponding level in
the system. If a device makes a request, it blocks the signal transmission to the
next device on the line; otherwise, it passes the signal on.
This causes the device closest to the processor to be the highest subpriority on
each request level.
1.3.1 Priority Transfer (PTR) Transaction (See Figure 1-6)
The signal sequence by which a device becomes selected as next bus master is the
priority transfer (PTR) bus operation. This operation does not actually transfer
bus control; it only selects a device as next bus master. The sequence of events is
as follows:
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