PDP11 PeripheralsHbk 1972 - Trailing-Edge

The bus master places address, control, and data information on the UNIBUS,
waits 150 ns, and then asserts MSYN. After a worst case propagation delay of 75
ns, the slave recognizes MSYN and clocks the data into its register. Since the 75ns
propagation delay includes the transmitter and receiver delays, the time required
to turn MSYN around into SSYN is literally O. Also, since the data preceded
MSYN by 150 ns (worst case skew is only 75 ns), there is ample preset time for
the data input to the slave device flip-flop register.
When the master sees SSYN, it clears its MSYN control (nominal time, 25 ns) and
then waits 75 ns before clearing or changing address, control, and data information.
Additional cycles may proceed at this time provided SSYN is cleared before
MSYN is again asserted. This means that a sustained DATa transfer rate of 400
ns/word may be maintained. This is equivalent to a transfer rate of 40 million
bits per second.
Figure 1-11 is a typical timing flow diagram for a DATI transfer. The slave device
logic is shown in Figure 1-12. The procedure for a DATI transfer is essentially the
same as for a DATa transfer with four exceptions:
a. The master asserts only address and control information.
b. The slave gates data onto the bus simultaneously with the return of SSYN.
c. The master must wait 75 ns (to allow for skew between SSYN and DATA) before
clearing MSYN and strobing data.
d. The slave clears data when it clears SSYN.
The DATI cycle allows sustained transfer rates of 450 ns-word which is equivalent
to 35.2 million bits second.
1.4.2 Time-Out Protection
A precaution must be taken when designing peripheral devices that gain control
of the bus for the purpose of transferring data to another element on the UNI­
BUS. Normally, such a device contains a bus address register, which is loaded by
the program as one of the initialization steps. This address must then be incremented
by the device upon completion of each data transfer. If the program
loads an erroneous address or if the register increments beyond the available
core memory in the existing system, no SSYN response is generated for the data
transfer. To prevent this problem from hanging up the system, it is recommended
that a 10- to 25-pS integrating one-shot be triggered each time the master device
asserts MSYN. If this one-shot times out before SSYN is received, the master
should stop the transfer by clearing MSYN, BBSY, and any other signals it has asserted.
The master should then set an error flag in its status register.
1.5 ADDRESS MAPPING
A PDP-Address Map is shown in Appendix A. Observe that, in the following discussion,
all addresses are numbered in octal. The letter K, which is normally used
to devote 1000 (decimal), is used in this discussion to denote 1024 (decimal).
The UNIBUS addresses 2'8 locations (262,144 '0 or 256K), and each location contains
eight bits. On the basic PDP-ll systems only 16 bits of address information
are under program control. This limits the processor to an address map of 64K locations.
Since the word length and bus width are two bytes, most bus operations
access two locations at once; the address supplied on the bus is that of the evennumbered
location, and the next higher odd location is selected as well. Byte op-
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