PDP11 PeripheralsHbk 1972 - Trailing-Edge

nel and low COY) for a transfer from the channel; a break state (BRK STATE) signal,
which is low when the secondary computer is in the break state; and three
timing signals transmitted by the channel control to indicate break and address
accepted (BRK ACPT), data accepted (DATA ACPT), and data available (DATA
AVAil).
3.7.2 Interface Description
The interface in Figure 3-12 operates as a cycle stealing device on a data channel
of another computer and responds as a slave device on the PDP-11 UNIBUS. The
primary purpose of this interface is to transfer data between two processors.
Therefore, no provision is made to directly control operation of the secondary
computer.
The interface structure includes the data paths between the two processors; the
address paths from the UNIBUS to the secondary processor; a block (BLK) register
(expandable to match the memory space of the secondary processor), which
modifies the address transmitted on the data channel in order for it to access one
of eight 4K word blocks; and the interface control logic, which determines the timing
and gating of the data and control signal flow.
M105
elK
DCCSR
OATA OUT
r------l
I
I
I
I
figure 3-12 PDP-11-to-Data Channel Interface (block diagram)
When the PDP-11 addresses a bus location in the seventh block of 4K words
(A =00110), the interface generates a BRK REQ signal. The address
used by the data channel is a 15-bit number assembled by transmitting the informationon
lines A < 12:01 > as the 12 least significant bits, and transmitting the
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