PDP11 PeripheralsHbk 1972 - Trailing-Edge

contents of the BLK register as the 3 most significant bits. The interface responds
to 4K word (8K byte) addresses on the UNIBUS, but can access 32K words in the
data channel. Only 4K words are accessible for any particular setting of the BLK
register.
3.7.3 Interface Operation
When performing transfers with the data channel computer, the PDp·11 first
loads the desired block number into the BLK register, which is addressed as a de·
vice register (A = 11111 and A equal to its assigned bus ad·
dress). The PDp·ll then addresses a location in the 4K block of UNIBUS ad·
dresses which have A =00110. The corresponding location in the 4K
block selected by the BLK register is selected by the data channel. A data transfer
is accomplished by issuing a BRK REQ signal, an address, and setting the DATA
DIR level; receiving a BRK ACPT pulse; gating data through the interface; and reo
ceiving either a DATA ACPT or a DATA AVAIL pulse to generate SSYN .
. 3.7.4 Interface Implementation
Figure 3·13 i'liustrates details of a possible control circuit for implementing the
PDP-ll to data channel interface. The BRK REQ flip-flop is set when the bus address
is in the specified 4K block and cleared by the BRK ACPT H pulse from the
data channel. The SSYNF flip-flop is set by eitt)er a DATA ACPT H or a DATA
AVAIL H pulse, depending on the direction of the data transfer. The SSYNF flipflop
is cleared when MSYN is cleared. The DATA AVAIL H pulse also clocks data
into a buffer register, which is gated to the bus when the SSYNF flip-flop is set.
This provides a data transfer to the bus. This implementation assumes that the
data channel computer operates with logic levels similar to the PDp·11. Thus, a
high ( + 3V), level is a logic 1 and a low (OV) level is a logic O.
3.8 PDP-llTO PDP-ll INTERFACE
The PDP-ll to PDP-ll interface permits devices on one PDP-ll UNIBUS to address
locations on a second PDP-ll UN IBUS. Two possible applications of this interface
are:
a. Connecting two PDP-ll processors so that one processor executes its own
program and also controls execution of programs by a second slave processor.
b. Monitoring operation of a UNIBUS system by a processor that is not in the
same system.
3.8.1 Interface Description and Operation
The PDp·ll to PDp·l1 interface (Figure 3·14) consists of one M7820 Interrupt
Control, one M 105 Address Selector Module, several sets of bus receivers and bus
drivers, and some control circuits. The M 105 Module is connected to the Primary
UNIBUS and the M7820 Module is connected to the secondary UNIBUS. The major
flow of data within the interface is from one UN IBUS, through bus receivers
and gated bus drivers, to the other UNIBUS. Data also flows from the primary
UNIBUS to the control circuit.
When the primary UNIBUS requests interface operation, the interface requests
control of the secondary UNIBUS, and the primary UNIBUS is connected to allow
data transfers with the secondary UNIBUS. The interface is designed to recognize
addresses in the seventh 8K (byte) field of primary UNIBUS addresses, and convert
them to addresses in any selected 8K (byte) field of addresses on the secondary
UNIBUS. This is equivalent to replacing one 8K field of bus addresses on the
primary UNIBUS with an 8K field of addresses from the secondary UNIBUS. The
field on the secondary UNIBUS is selected by loading a field select register in bits
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