PDP11 PeripheralsHbk 1972 - Trailing-Edge

BIT
15
NAME
Error
14-8 Unused
7 Done
6 Interrupt Enable
5 Fix
4 Up/Down
3 Mode
2,1 Rate Select
o Run
DESCRIPTION
Detects an error condition in Mode 1 operation
where a second underflow or over·
flow of the COUNTER occur before the interrupt
of a preceding underflow has been
serviced. This bit is cleared by program
It cannot be set by program.
Indicates an underflow has occurred. Set
on underflow or overlfow and cleared by
program' or INIT.
Provides a signal to the interrupt control
logic of the KWll-P to allow generation of
a bus request of COUNTER underflow or
overflow. Set by progra m and cleared by
program or INIT.
Maintenance bit, allowing single clocking
of the counter. Setting clocks the counter
by one count. CLOCKED by program control.
Write only.
Selects count-up or count-down input of
the COUNTER. When cleared, as for normal
interrupt operation (single or repeated),
the count-down input is selected.
When set, the count-up input is used.
Selects one of two interrupt modes. When
set, enables MODE 1: the repeated interrupt
mode. When cleared, MODE 0 is selected
for single interrupts. Set by program
and cleared by program or INIT.
The RATE SELECT bits provide the selection
of 1 of 4 available clock rates. The
two bits are set by program and cleared by
program or INIT.
BIT 02
o
o
1
1
BIT 01
o
1
o
1
Rate
lOOK Hz
10K Hz
Line Freq
External
The RUN BIT controls the strobe input of
the count rate multiplexer. When set, it
gates the selected rate to the clock input
of the COUNTER. RUN is cleared on underflow
or overflow in MODE 0 operation
and by IN IT in al/ other cases.
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