PDP11 PeripheralsHbk 1972 - Trailing-Edge
PDP11 PeripheralsHbk 1972 - Trailing-Edge
PDP11 PeripheralsHbk 1972 - Trailing-Edge
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a. Master sets C =00 for DATI or C=01 for DATlP, and sets<br />
A to specify the slave address.<br />
b. Master waits 150 ns minimum: 75 ns to allow for worst case signal skew on<br />
the UNIBUS plus 75 ns for slave to decode address.<br />
NOTE<br />
This guarantees that at the output :of the slave's bus<br />
receivers that A and C will precede<br />
MSYN" by 75 ns min.<br />
c. Master waits for bus to become inactive since SSYN may still be asserted from<br />
a previous cycle.<br />
d. Master asserts MSYN<br />
NOTE<br />
This condition is automatically satisfied when first becoming<br />
bus master since SSYN must be negated before<br />
BBSY can be asserted (see M7820 circuit).<br />
e. When the selected slave sees its address and MSY.N, the slave device prepares<br />
the data for transmission to the master. For devices such as memory, this<br />
means performing a read cycle; for flip-flop registers, the data is available immediately_<br />
f. When data is available, the slave places data on 0 and asserts<br />
SSYN_ If the slave is a destructive read-out device, it enters a restore cycle if<br />
the command was a DATI; for a DATIP, the slave can set a pause flag and wait<br />
for the subsequent DATO or DATOB with the modified data before perfoming<br />
a write cycle. The SSYN response must be made within ?5/LSec.<br />
g. The master receives SSYN and waits 75 ns minimum to allow for skewing of<br />
data plus any additional time the master may need for internal gating.<br />
h. Master strobes in data from 0.<br />
i. When the data has been accepted by the master device, it drops MSYN.<br />
j. After 75 ns minimum wait, the master removes or alters the A and C lines. If<br />
another DATI follows, then the master repeats the above sequence starting at<br />
. step a. If an output operation follows, the next cycle starts at step a. of the<br />
DATO or DA TOB operation. If this is the last bus cycle of the master's operation<br />
and when the A and C lines are all clear, then the master clears BBSY<br />
and relinquishes bus control.<br />
k. The slave sees the negation of MSYN and removes data from the D lines and<br />
negates SSYN.<br />
1.2.3 DATO and DATOS Bus Transactions (See Figure 1·5)<br />
Because all data transfers are with reference to the master device, a data out<br />
(DATO) indicates data transfer from the master to the slave.<br />
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