B. P. Lathi, Zhi Ding - Modern Digital and Analog Communication Systems-Oxford University Press (2009)

7.4 Scrambling 357
Figure 7.20 shows a typical scrambler and descrambler. The scrambler consists of a feedback
shift register, and the matching descrambler has a feedforward shift register, as shown
in Fig. 7.20. Each stage in the shift register delays a bit by one unit. To analyze the scrambler
and the matched descrambler, consider the output sequence T of the scrambler (Fig. 7.20a). If
S is the input sequence to the scrambler, then
(7.47)
where D represents the delay operator; that is, D n T is the sequence T delayed by n units. Now,
recall that the modulo 2 sum of any sequence with itself gives a sequence of all Os. Adding
(D 3 EB D 5 )T to both sides of Eq. (7.47), we get
S = T EB (D 3 EB D 5 )T
= [l EB (D 3 EB D 5 )] T
= (1 EB F)T (7.48)
where F = D 3 EB D 5 .
To design the descrambler at the receiver, we start with T, the sequence received at the
descrambler. From Eq. (7.48), it follows that
T EB FT = T EB (D 3 EB D 5 )T = S
This equation, in which we regenerate the input sequence S from the received sequence T, is
readily implemented by the descrambler shown in Fig. 7.20b.
Note that a single detection error in the received sequence T will affect three output bits
in R. Hence, scrambling has the disadvantage of causing multiple errors for a single received
bit error.
Example 7.2 The data stream 101010100000111 is fed to the scrambler in Fig. 7.20a. Find the scrambler
output T, assuming the initial content of the registers to be zero.
From Fig. 7.20a we observe that initially T = S, and the sequence S enters the register
and is returned as (D 3 EB D 5 )S = FS through the feedback path. This new sequence FS
again enters the register and is returned as F 2 S, and so on. Hence
T = S EB FS EB F 2 S EB F 3 S EB · · ·
= (1 EBF EBF 2 EBF 3 EB · ·· )S
(7.49)
Recognizing that
F = D 3 EBD 5
we have
Because modulo-2 addition of any sequence with itself is zero, D 8 EB D 8 = 0, and