B. P. Lathi, Zhi Ding - Modern Digital and Analog Communication Systems-Oxford University Press (2009)

686 DIGITAL COMMUNICATIONS UNDER LINEARLY DISTORTIVE CHANNELS
Figure 12.7
Equivalent
structure of
fractionally
spaced
equalizers (FSE).
F1 (z)
FSE
d[k]
Hm (Z)
12.4.2 FSE Designs
Based on the SIMO representation of the FSE in Fig. 12.7, one FSE filter is provided for each
subsequence Zi [k ]. In fact, the actual equalizer is a vector of filters
M
Fi(z) = L.ft [k]z - k
k=O
l= l, ... ,m (12.49)
The m filter outputs are summed to form the stationary equalizer output
m
M
y[k] = L Lfi[n]zi [k - n] (12.50)
i=l n=O
Given the linear relationship between equalizer output and equalizer parameters, any TSE
design c1iterion can be generalized to the FSE design.
ZF Design
To design a ZF FSE, the goal is to eliminate all ISI at the input of the decision device. Because
there are now m parallel subchannels, the ZF filters should satisfy
m
C(z) = L Fi (z)H; (z) = z - u (12.51)
i=l
This zero-forcing condition means that the decision output will have a delay of integer u.
A closer observation of this ZF requirement reveals its connection to a well-known equality
known as the Bezout identity. In the Bezout identity, suppose there are two polynomials of
orders up to L.
L
A1(z) = I: auz - ;
i=O
L
and A2 (z) = I: a2,;z - i
i=O