6th European Conference - Academic Conferences

Michael Bilzor
states, from which we constructed a full finite state machine (of control signal states) and identified all
the legal state-to-state transitions. Some of the ZPU's internal states and are shown in Figure 6.
Figure 4: Processor and system configuration without execution monitor
Figure 5: Processor and system configuration with execution monitor added
Figure 6: Some of the ZPU processor internal control states
The ZPU monitor accesses the identified control signals through VHDL "ports". In a physical 3D
design, these signals would transit from the target layer to the monitor layer by through-silicon vias
(TSVs) or some other 3D joining method. This mapping might occur at the 3D floorplanning stage,
before the netlist files have been synthesized into mask database files for each layer. Since this ZPU
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