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Michael Bilzor Figure 7: The processor executed normally, and no anomalies were detected Figure 8: The first processor anomaly was active, and was detected by the monitor Figure 9: The second processor anomaly was active, and was detected by the monitor The monitor's transition table had 112 records in it, to cover the 112 allowable transitions among the 23 unique internal processor states. These are reasonably small numbers to implement in a monitor, but we are also interested in the growth of the size of the monitor, as the target processor becomes more complex. Recall from Section 5 that a standard circuit's voltage, as described in VHDL, can represent one of 9 discrete values. For n circuits, then, we would expect 9 n possible signal permutations - an impractically large number, if the state machine must have 9 n states, one for each permutation. We will explore in future research whether the actual number of required signal permutations, and hence monitor states, is typically much smaller, as was the case in this example. We synthesized the design, using a Virtex-5 FPGA target, in two different configurations - the processor architecture alone, and the processor architecture with the monitor. In both cases, the maximum design speed was 228Mhz, indicating that adding the monitor did not impose a speed performance limit on the processor. 8. Conclusions The following are some of the limitations of this research: The techniques illustrated are focused on only one of the categories of malicious inclusion from the taxonomy described earlier; detection and mitigation techniques should be developed for the other types as well, and this is an open research area. The Execution monitor's performance must not limit the performance of the target processor which it monitors. For example, the maximum clock speed of the EM should be at least as fast as the maximum intended clock speed of the target processor. The power, area, and heat requirements of the monitor should not exceed the practical limits of the overall 3D design. Also, the clock-cycle latency between MI activation and detection should be small enough to permit effective correction. We plan to evaluate 3D-EM designs further, using these performance measures, in the future. From our preliminary work on the ZPU 3D-EM design, we reached the following conclusions: Designing and simulating the operation of a basic 3D monitor for a simple processor design is feasible. However, the physical design space for 3D monitors needs further exploration, and monitors for more complex processors should be developed. As expected, simple deviations from the processor's specified instruction-control behavior can be detected at runtime. The 3D Execution monitor is the first hardware-based approach with the potential for identifying processor MIs both during testing and during real-time, fielded operation - an important advantage 296
Michael Bilzor over testbench methods, since delayed triggers may cause an MI to be inactive during predeployment testing. 9. Future work For this demonstration, we selected the control signals and developed the stateful representation manually. In future experiments, we hope to work on methods whereby the microarchitectural control signals can be automatically identified, and the monitor constructed automatically or semiautomatically (or identify any reasons why the process cannot be automated). We would like to design a monitor for a register-based processor with one or more data buses, in order to compare it with monitoring a stack-based processor like the ZPU. We would also like to design processor anomalies which accomplish some more meaningful subversions. Finally, we wish to test whether the monitor can detect unknown MIs, designed by third parties unfamiliar with the monitor construction. It would be useful to scale up the 3D Execution monitor experiments to more complex processor designs, with modern features like pipelined and speculative execution, multithreading, vector operations, virtualization support, and multi-core. Acknowledgements This research was funded in part by National Science Foundation Grant CNS-0910734. References Adee, S., (2008) "The Hunt for the Kill Switch", [online] IEEE Spectrum, May 2008, http://spectrum.ieee.org/semiconductors/design/the-hunt-for-the-kill-switch Agrawal, D., Baktir, S., Karakoyunlu, D., Rohatgi, P., and Sunar, B. (2007) "Trojan Detection Using IC Fingerprinting", 2007 IEEE Symposium on Security and Privacy. Defense Science Board (2005). Report of the 2005 Defense Science Board Task Force on High Performance Microchip Supply, Office of the Undersecretary of Defense for Acquisition, Technology, and Logistics. Iman, S. (2008) Step-by-Step Functional Verification with SystemVerilog and OVM, Hansen Brown Publishing, San Francisco. Jin, Y. and Makris, Y. (2008) "Hardware Trojan Detection Using Path Delay Fingerprint", Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust. Jin, Y., Kupp, N., and Makris, Y. (2009) "Experiences in Hardware Trojan Design and Implementation", Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust. King, S., Tucek, J., Cozzie, A., Grier, C. Jiang, W., and Zhou, Y. (2009) "Designing and Implementing Malicious Hardware", Proceedings of the IEEE International Workshop on Hardware Oriented Security and Trust. Markoff, J. (2009) "Old Trick Threatens Newest Weapons", [online], New York Times, 27 October. http://www.nytimes.com/2009/10/27/science/27trojan.html?_r=2. McCormack, Richard (2008) "DoD Broadens 'Trusted' Foundry Program to Include Microelectronics Supply Chain", Manufacturing & Technology News, Thursday, 28 February. Mysore, S., Agrawal, B., Srivastava, N., Lin, S., Banerjee, K., and Sherwood, T. (2006) "Introspective 3D Chips", 2006 International <strong>Conference</strong> on Architectural Support for Programming Languages and Operating Systems. Nystedt, D. (2007) "Intel Got its New China Fab for a Bargain, Analyst Says", [online] CIO.com, http://www.cio.com/article/101450/Intel_Got_Its_New_China_Fab_for_a_Bargain_Analyst_Says OpenCores.org (2010), [online] http://opencores.org. Pellerin, D., and Taylor, D. (1997) VHDL Made Easy, Prentice Hall, Upper Saddle River, NJ. Puttaswany, K., and Loh, G., (2006) "Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology", Proceedings of the 2006 Emerging VLSI Technologies and Architectures, Vol. 00, March. Rad, R., Plusquellic, J., and Tehranipoor, M. (2008) "Sensitivity Analysis to Hardware Trojans Using Power Supply Transient Signals", 2008 IEEE International Workshop on Hardware Oriented Security and Trust. Schneider, F. (2000) "Enforceable Security Policies", ACM Transactions on Information and System Security, Vol. 3, No. 1, February, pp 30-50. Tehranipoor, M. and Koushanfar, F. (2010) "A Survey of Hardware Trojan Taxonomy and Detection", IEEE Design and Test of Computers, vol. 27, issue 1, January/February, pp10-24. Valamehr, J., Tiwari, M., Sherwood, T., Kastner, R., Huffmire, T., Irvine, C., and Levin, T., (2010) Hardware Assistance for Trustworthy Systems through 3-D Integration, Proceedings of the 2010 Annual Computer Security Applications <strong>Conference</strong> (ACSAC), Austin, TX, December. Yinung, F. (2009) "Challenges to Foreign Investment in High-Tech Semiconductor Production in China", United States International Trade Commission, Journal of International Commerce and Economics, May. 297
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The Proceedings of the 6th Internat
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Contents Paper Title Author(s) Page
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Preface These Proceedings are the w
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Biographies of contributing authors
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Department of Computer Science, IQR
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Using the Longest Common Substring
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Jaime Acosta Some techniques that u
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Jaime Acosta assigned by an anti-vi
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Jaime Acosta Cormen, T.H., Leiserso
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Hind Al Falasi and Liren Zhang tran
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Hind Al Falasi and Liren Zhang ther
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Hind Al Falasi and Liren Zhang the
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Edwin Leigh Armistead and Thomas Mu
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Deception Operations Security (OPS
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The Uses and Limits of Game Theory
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3. Limits to using game theory 3.1
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Merritt Baer Effective cyberintrusi
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Merritt Baer 1.5), there seems to b
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Merritt Baer Report of the Defense
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Ivan Burke and Renier van Heerden F
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Ivan Burke and Renier van Heerden a
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Marco Carvalho et al. systems start
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Marco Carvalho et al. Benatallah, 2
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Marco Carvalho et al. Figure 4: Sta
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Marco Carvalho et al. Sorrels, D.,
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Manoj Cherukuri and Srinivas Mukkam
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Mecealus Cronkrite et al. trivial.
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Mecealus Cronkrite et al. socially
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Mecealus Cronkrite et al. The views
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Vincent Garramone and Daniel Likari
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Stephen Groat et al. Sections 4 and
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Stephen Groat et al. probability fo
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Stephen Groat et al. host. In this
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Stephen Groat et al. changing addre
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Marthie Grobler et al. leadership,
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Marthie Grobler et al. apply to sta
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Marthie Grobler et al. 6. Working t
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Cyber Strategy and the Law of Armed
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Ulf Haeussler Alliance and Allies r
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Ulf Haeussler following the invocat
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Ulf Haeussler NCSA (2009) NCSA Supp
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Karim Hamza and Van Dalen of respon
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Karim Hamza and Van Dalen From a mi
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Karim Hamza and Van Dalen productiv
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Intelligence-Driven Computer Networ
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Eric Hutchins et al. of defensive a
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Eric Hutchins et al. Defenders can
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Eric Hutchins et al. Equally as imp
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Eric Hutchins et al. X-Mailer: Yaho
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Eric Hutchins et al. Received: (qma
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Eric Hutchins et al. U.S.-China Eco
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Saara Jantunen and Aki-Mauri Huhtin
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Brian Jewell and Justin Beaver In t
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Brian Jewell and Justin Beaver Figu
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4. Evaluation Brian Jewell and Just
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Brian Jewell and Justin Beaver othe
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Detection of YASS Using Calibration
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Kesav Kancherla and Srinivas Mukkam
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M M M Su−2 Sv ∑∑ u= 1 v= 1 h(
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5.2 ROC curves Kesav Kancherla and
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Developing a Knowledge System for I
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Louise Leenen et al. We distinction
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Louise Leenen et al. There is growi
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3.1 Needs analysis Louise Leenen et
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Louise Leenen et al. Kroenke, D.M.
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Jose Mas y Rubi et al. As we can se
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Figure 2: CALEA forensic model (Pel
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Jose Mas y Rubi et al. Table 2: Com
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Jose Mas y Rubi et al. Another pend
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Tree of Objectives Acknowledgements
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Secure Proactive Recovery - a Hardw
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Ruchika Mehresh et al. implementing
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Ruchika Mehresh et al. The coordina
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Ruchika Mehresh et al. multiplicati
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Ruchika Mehresh et al. Table 2: App
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2. Network infiltration detection D
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David Merritt and Barry Mullins on
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David Merritt and Barry Mullins Ess
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David Merritt and Barry Mullins Dev
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Muhammad Naveed Pakistan Computer E
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Muhammad Naveed Table 10: Aggressiv
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Muhammad Naveed 2006 Tcp Open Mysql
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Muhammad Naveed 8009 Tcp Open Ajp13
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Muhammad Naveed Austalian Taxation
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Alexandru Nitu world and bring it i
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Alexandru Nitu Article 51 restricts
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Alexandru Nitu As IW strategy and t
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Cyberwarfare and Anonymity Christop
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Christopher Perr attacks again help
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Christopher Perr about the current
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Catch me if you can: Cyber Anonymit
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David Rohret and Michael Kraft reve
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David Rohret and Michael Kraft sary
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Data (Evidence) Removal Shield Davi
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Neutrality in the Context of Cyberw
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Julie Ryan and Daniel Ryan 18th cen
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Julie Ryan and Daniel Ryan “Decla
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Julie Ryan and Daniel Ryan von Glah
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Harm Schotanus et al. In the remain
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Harm Schotanus et al. 2.3.1 Secure
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Harm Schotanus et al. In this setup
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Harm Schotanus et al. the label (by
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Harm Schotanus et al. these aspects
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Maria Semmelrock-Picej et al. they
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Maria Semmelrock-Picej et al. User
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Maria Semmelrock-Picej et al. SPIKE
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Page 299 and 300: Michael Bilzor a diverse base of U.
Page 301 and 302: Michael Bilzor In our current exper
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Page 309 and 310: Evan Dembskey and Elmarie Biermann
Page 317 and 318: Theoretical Offensive Cyber Militia
Page 319 and 320: Rain Ottis Last, but not least, it
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Page 327 and 328: Large-Scale Analysis of Continuous
Page 329 and 330: References William Acosta Abadi, D.
Page 331 and 332: Natarajan Vijayarangan top box unit
Page 333 and 334: Natarajan Vijayarangan The proposed
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