IGCAR : Annual Report - Indira Gandhi Centre for Atomic Research

IGC
Annual Report 2007
modules was configured and
optimized for using with
phoswich based plutonium lung
monitor. The PSD electronics
has not altered any of the
spectrum parameters like shape
of spectrum, peak position and
FWHM. The figure of merit
obtained for the timing
spectrum is 3.0. The
background reduction obtained
is 97% with PSD and with a
signal loss of only 4%. This
effective background reduction
improves the MDA values by
factor 2.
V.C.6. Digital Design Verification
For safety systems of nuclear
reactors, electronic hardware
systems are preferred to
software systems wherever
feasible. This is so because, for
software, terms like reliability
and quality are difficult to
quantify. EID has designed and
developed a number of
complex digital circuits using
Very Large Scale Integration
(VLSI) techniques for the Safety
Systems of PFBR. These designs
have been implemented using
Very High Speed Integrated
Circuit (VHSIC) Hardware
Description Language (VHDL).
These circuits have been tested
extensively and found to
function well. But here, since
the hardware design was also
done using a HDL, it was
thought necessary to perform
extensive verification of the
HDL code used in the design.
Therefore, a collaboration
project was undertaken with
Indian Institute of Technology,
Madras (IIT-M) for the
development of generic tools
for the verification of VLSI
designs made at centre. As part
of the project, six VHDL designs
were taken up for verification.
The first phase included
preparation of detailed design
specifications, finalizing the test
plans and providing other
required inputs to the IIT-M
team. For each design, a test
plan was first prepared. After a
few iterations to ensure that the
test plan would really cover all
the areas that need to be
tested, it was approved by the
IGCAR team. Following this
was the design verification
phase.
The verification of the designs
was performed using e
verification language in
Specman Elite environment.
The various components of the
environment are shown in
Fig.1.The`e ’verification
Language can be used to
construct components to do the
following functions.
Generation: e automates the
generation of stimuli based on
the constraints provided.
Driving stimulus: e provides a
simulator interface and the
necessary mechanism to drive
the generated test vectors into
the DUT.
Collecting output: After the
stimulus is applied to the DUT,
output is produced from the
DUT. e provides a simulator
interface and the necessary
mechanism to receive data
from the DUT
Data checking: Data value
checks compare the output
data values against the
expected data. Temporal
assertions monitor the
functional protocol at important
interfaces. Temporal checking
constructs are used to build
protocol monitors.
Coverage: Functional
coverage tells the verification
engineer if the test plan goals
have been met.
134 ENABLING TECHNOLOGIES