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Thesis - Leigh Moody.pdf - Bad Request - Cranfield University

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Chapter 3 / Sensors<br />

_ _<br />

INPUT; AA, & ADC OUTPUTS<br />

1<br />

0.8<br />

0.6<br />

0.4<br />

0.2<br />

0<br />

-0.2<br />

-0.4<br />

-0.6<br />

-0.8<br />

-1<br />

0 200 400 600 800 1000<br />

TIMESTEP ( MSEC )<br />

Figure 3-16 : Digitised Analogue Output<br />

The filtered input signal is quantised with a Least Significant Bit (LSB) of<br />

0.00627 representing the ADC reference voltage scaling. This is then<br />

clipped to 0.8 of the input signal due to internal word length limitations (a<br />

bad design but one chosen to illustrate the effect).<br />

1<br />

floor(u[1]/7*SN_AQ)<br />

ceil(u[1]/7*SN_AQ)<br />

1<br />

-1<br />

2<br />

-2<br />

4<br />

-4<br />

3.2-25<br />

ZOH<br />

SN_AQ<br />

Figure 3-17 : ADC/DAC Noise Model<br />

The ADC quantised noise was disabled. Figure 3-16 clearly shows the<br />

expected the combined A/A and ADC time delay of 0.04 s that may be<br />

compensated for in a state observer, or in the sensor itself. ADC noise<br />

levels of 1 LSB often quoted but these are usually optimistic, even carefully<br />

design results in noise affecting the lowest 3 bits, i.e. noise of up to 7*LSB.<br />

1

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