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Appendix I / Utilities / General
_ _
22.2 General Utilities
22.2.1 System Clock Update
Provision for up to 50 system clocks of which 23 are currently in use, each
initialised to a different cyclic rate in CONSTANTS. The Master Clock runs
at 16 kHz from which the sub-system clocks are derived. Thus the
simulation reference time interval (∆tR) has a fixed value of 62.5 µs. To
prevent time quantisation only clocks that are 16 kHz dividers are permitted.
CLOCK
( n )
Table 22-1 : Simulation Clock Frequencies
RATE
ωC (Hz)
CLOCK
( n )
22.2-1
RATE
ωC (Hz)
CLOCK
( n )
RATE
ωC (Hz)
1 8000 9 400 17 20
2 4000 10 200 18 10
3 3200 11 125 19 8
4 2000 12 100 20 5
5 1600 13 80 21 4
6 1000 14 50 22 2
7 800 15 40 23 1
8 500 16 25 NUPDAT := 23
The clocks are synchronised during initialisation so that their leading edges
are aligned. When the clocks are reset this represents their leading edge to
which all simulation models are latched. During initialisation the clock
rates in Table 22-1 are converted into the number of simulation reference
cycles in I_TIMING. These indices control the clock reset and are stored in
the 2 nd column of array UPDATE(n,2) U(n,2), where (n) is the clock
identifier. For the time period after initialisation [ 0 , ∆tR [ ,
ω
CLK
ω
C
<
nint
( n , 1 ) : = 1
U k : = 1
⎛
⎜
⎝ ω
Equation 22.2-1
1
⋅ ∆t
( ) ( ) ⎟ 1 ∆t
⇒ U n , 2 : = nint ⎜
R
CLK
( 1 ∆t
) ⇒ U ( n , 2 ) : = nint ( 1 t )
≥ n int
∆
R
R
⎞
⎠
Equation 22.2-2
R
Equation 22.2-3
Vector TUPDAT(n) T(n) remains constant once initialised and contains the
time interval between clock leading edges,