Retinal Prosthesis Dissertation - Student Home Pages

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Table 1 Correlation between fps and AER packet frequency ................................................................ 21 Table 2 `and’ and `or’ truth tables .......................................................................................................... 27 Table 3 `xor’ and `nxor’ truth tables ....................................................................................................... 28 Table 4 row and column addressing ...................................................................................................... 43 Table 5 Receptive ON/OFF operation .................................................................................................. 64 Table 6 Tspike related to fps .................................................................................................................... 81 Table 7 examples of clocking hierarchy ................................................................................................. 82 Table 8 short AER format ...................................................................................................................... 85 Table 9 example correspondences ........................................................................................................ 86 Table 10 electrode requirement ............................................................................................................. 92 Table 11 clocking calculations ............................................................................................................... 95 Table 12 simulation clocking .................................................................................................................. 95 Table 13 receiver calculations ............................................................................................................... 99 Table 14 Receiver chip FPGA resource data ...................................................................................... 101 Table 15 Control signals to enable DAC .............................................................................................. 107 Table 16 IGLOO product table ............................................................................................................. 115 Table 17 image size versus bit length .................................................................................................. 115 ix of ix
Chapter 1 Introduction/research aim The approach to be taken for this work is to determine and then decide how to implement a retinal prosthesis capable of restoring sufficient vision to a person suffering visual impairment to improve their quality of life. My goal here is not to implant an actual prosthesis but to evaluate ideas about the way to efficiently communicate the signals to the prosthesis. The boundaries of my study are to behaviourally programme in a Virtex 5 FPGA[16] a test image of 1024 pixels and structurally implement; in terms of VHDL programming, using the Xilinx ISE platform an image of 16 pixels as proof of concept. The limitation of the structural implementation is that the output of the FPGA will further require a post processing interface i.e. the microstimulator or driver portion [17-22] which typically resides on the retinal implant itself and enables the outputted signals from the FPGA to control the timing of the charge being delivered to the electrodes of the retinal implant array [23-30]. Although ten percent of the population suffer from visual impairment; so in the UK six million people, only ten percent of those suffer from AMD (age related macular degeneration) [Aside young people can also suffer from this condition] and RP (retinitis pigmentosa) a family of related diseases to which this study applies. Although this represents less than one million people in the UK clearly the European/worldwide market is much bigger. It also bears saying that the gift of sight is priceless for each person affected to a greater or lesser degree. 1.1 Introductory Literature Review The following subsections pick out the differing approaches from the relevant literature and also the commonality of those approaches where this exists. 10 of 200
Page 1 and 2: An Address Event Representation (AE
Page 3 and 4: Abstract\Foreword This document pro
Page 5 and 6: Contents An Address Event Represent
Page 7 and 8: --Appendix E FPGA Outputs .........
Page 9: Figure 48 receiver rtl_16 .........
Page 13 and 14: foveola (fovea pit) there is a one
Page 15 and 16: NB that the photoreceptors of the f
Page 17 and 18: electrodes to be driven implies sti
Page 19 and 20: Typically AER is used as a multi se
Page 21 and 22: Real time - innerpulse relationship
Page 23 and 24: the post processing stage of this w
Page 25 and 26: Appendix C: FPGA Sender chip Append
Page 27 and 28: Red (660nm) R / G Red ( 620750nm )
Page 29 and 30: 1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
Page 31 and 32: Adaptive linear combiner w 0 1 Let
Page 33 and 34: is correct (one class) and -1 (the
Page 35 and 36: x2 Linear separation 1.00 0.90 0.80
Page 37 and 38: This is also the Cartesian co-ordin
Page 39 and 40: 2.4 Comparison to Frame Based Repre
Page 41 and 42: Typical GOP structure (Typically an
Page 43 and 44: point is an event occurs for spike
Page 45 and 46: 2.5.1 Files in Appendix A “ycut.m
Page 47 and 48: MPEG-2 setup AER setup Camera Camer
Page 49 and 50: 2.6.2 FPGA representation of epi_re
Page 51 and 52: Chapter 3 Concepts An epiretinal im
Page 53 and 54: AER Transmission lines INPUT image
Page 55 and 56: electrical pulse generated is calle
Page 57 and 58: Figure 25 Retinal colour processing
Page 59 and 60: cells to modulate this luminance pa
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L+ M- + - R-G G-R B-Y Y-B Note: L(r
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3.6.2 Retinal operations Light reac
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quantified by number of cycles pres
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(Where * is the convolution operato
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T frame C * R * M p Tpacket i.e. Tp
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e relaxed and from (2) the temporal
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one tw o three four five six seven
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3.8.1 Other test images For other b
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Tspike (4ms) Ispike (16ms: interspi
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INDIGO ORANGE YELLOW MAGENTA CYAN B
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4.1 Sender concepts From chapter on
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pixel must equate to 0.02/1024 i.e.
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Clocking hierarchy (32 by 32 image)
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the number of address bits will alt
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Translation report, (3) Map report,
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90 of 200 CLKIN_IN RST_IN pixelcloc
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incorporate colour planes for each
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Chapter 5 Receiver chip The followi
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5.2 Power Analysis Xilinx FPGAs hav
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98 of 200 produce_wire _outputs Ins
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5.5.1 Incoming (short) AER stream T
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Receiver Red plane r1 DAC (4-bit) T
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5.8.2 Electrode size and positionin
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sequence of wiring from the receive
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does this is to inject an equivalen
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6.2.2 Envisaged retinal array This
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a monochrome camera in this space i
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632mW) thus extending battery life
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For the implemented/structural case
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The sender and receiver circuitry p
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Bibliography 1. Woodburn R. Murray
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38. Banks, D.J., P. Degenaar, and C
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74. Freeman, J.A., Skapura, D. M.,
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109. Weiland, J.D., et al. Progress
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141. Indiveri G. Chicca E. Douglas
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172. Singh, P.R., et al. A matched
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206. Stieglitz, T., et al. Developm
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xmixedsource; numberOfFrames = 8; f
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%check {k} =imread (['D:\abc\subima
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%Two for loops the first (outer loo
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%Row break rr6c1=000; rr6c2=000; rr
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--Appendix B FPGA Test setup librar
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stream_blue_pulse_count: out std_lo
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DVI_XCLK_P clock_25MHz, spike_cloc
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use IEEE.STD_LOGIC_UNSIGNED.ALL; --
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--Appendix C FPGA Sender chip libra
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-- else -- resit '1', CLKDV_OUT =>
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FPGA Receiver (structural) chip --A
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FPGA Receiver (structural) chip --E
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FPGA Receiver (structural) chip --r
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FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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