Retinal Prosthesis Dissertation - Student Home Pages

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--------------------------------------------------- FF Toggle Rate (%) | 12.5 | I/O Toggle Rate (%) | 12.5 | Output Load (pF) | 5.0 | I/O Enable Rate (%) | 100.0 | BRAM Write Rate (%) | 50.0 | BRAM Enable Rate (%) | 25.0 | DSP Toggle Rate (%) | 12.5 | Power summary | I(mA) | P(mW) | ---------------------------------------------------------------- Total estimated power consumption | | 637.79 | --- Total Vccint 1.00V | 424.29 | 424.29 | Total Vccaux 2.50V | 83.40 | 208.50 | Total Vcco25 2.50V | 2.00 | 5.00 | --- Clocks | | 3.06 | DCM | | 68.00 | IO | | 0.15 | Logic | | 0.01 | Signals | | 0.00 | --- Quiescent Vccint 1.00V | 406.57 | 406.57 | Quiescent Vccaux 2.50V | 75.40 | 188.50 | Quiescent Vcco25 2.50V | 2.00 | 5.00 | Post-PAR Static Timing Report example Release 11.4 Trace (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise C:/MATLAB/R2009a/fpga_ver_11/hyper_receive_16_pix/hyper_receive_16_pix.ise -intstyle ise -e 3 -s 3 -xml top_wrapper.twx top_wrapper.ncd -o top_wrapper.twr top_wrapper.pcf Design file: top_wrapper.ncd Physical constraint file: top_wrapper.pcf Device,package,speed: xc5vlx50t,ff1136,-3 (PRODUCTION 1.66 2009-11-16, STEPPING level 0) Report level: error report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2698 - No timing constraints found, doing default enumeration. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 187 of 200
Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock USER_CLK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ USER_CLK | | | | 1.715| ---------------+---------+---------+---------+---------+ Analysis completed Tue May 25 13:37:16 2010 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 220 MB Total REAL time to Trace completion: 18 secs Total CPU time to Trace completion: 18 secs 188 of 200
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
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1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
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Adaptive linear combiner w 0 1 Let
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is correct (one class) and -1 (the
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x2 Linear separation 1.00 0.90 0.80
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This is also the Cartesian co-ordin
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2.4 Comparison to Frame Based Repre
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Typical GOP structure (Typically an
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point is an event occurs for spike
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2.5.1 Files in Appendix A “ycut.m
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MPEG-2 setup AER setup Camera Camer
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2.6.2 FPGA representation of epi_re
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Chapter 3 Concepts An epiretinal im
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AER Transmission lines INPUT image
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electrical pulse generated is calle
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Figure 25 Retinal colour processing
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cells to modulate this luminance pa
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L+ M- + - R-G G-R B-Y Y-B Note: L(r
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3.6.2 Retinal operations Light reac
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quantified by number of cycles pres
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(Where * is the convolution operato
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T frame C * R * M p Tpacket i.e. Tp
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e relaxed and from (2) the temporal
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one tw o three four five six seven
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3.8.1 Other test images For other b
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Tspike (4ms) Ispike (16ms: interspi
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INDIGO ORANGE YELLOW MAGENTA CYAN B
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4.1 Sender concepts From chapter on
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pixel must equate to 0.02/1024 i.e.
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Clocking hierarchy (32 by 32 image)
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the number of address bits will alt
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Translation report, (3) Map report,
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90 of 200 CLKIN_IN RST_IN pixelcloc
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incorporate colour planes for each
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Chapter 5 Receiver chip The followi
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5.2 Power Analysis Xilinx FPGAs hav
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98 of 200 produce_wire _outputs Ins
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5.5.1 Incoming (short) AER stream T
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Receiver Red plane r1 DAC (4-bit) T
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5.8.2 Electrode size and positionin
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sequence of wiring from the receive
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does this is to inject an equivalen
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6.2.2 Envisaged retinal array This
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a monochrome camera in this space i
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632mW) thus extending battery life
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For the implemented/structural case
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The sender and receiver circuitry p
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Bibliography 1. Woodburn R. Murray
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38. Banks, D.J., P. Degenaar, and C
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74. Freeman, J.A., Skapura, D. M.,
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109. Weiland, J.D., et al. Progress
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141. Indiveri G. Chicca E. Douglas
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172. Singh, P.R., et al. A matched
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206. Stieglitz, T., et al. Developm
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xmixedsource; numberOfFrames = 8; f
Page 137 and 138: %check {k} =imread (['D:\abc\subima
Page 139 and 140: %Two for loops the first (outer loo
Page 141 and 142: %Row break rr6c1=000; rr6c2=000; rr
Page 143 and 144: --Appendix B FPGA Test setup librar
Page 145 and 146: stream_blue_pulse_count: out std_lo
Page 147 and 148: DVI_XCLK_P clock_25MHz, spike_cloc
Page 149 and 150: use IEEE.STD_LOGIC_UNSIGNED.ALL; --
Page 151 and 152: --Appendix C FPGA Sender chip libra
Page 153 and 154: -- else -- resit '1', CLKDV_OUT =>
Page 155 and 156: FPGA Receiver (structural) chip --A
Page 157 and 158: FPGA Receiver (structural) chip --E
Page 159 and 160: FPGA Receiver (structural) chip --r
Page 161 and 162: FPGA Receiver (structural) chip blu
Page 163 and 164: FPGA Receiver (structural) chip con
Page 165 and 166: FPGA Receiver (structural) chip --s
Page 167 and 168: FPGA Receiver (structural) chip --
Page 169 and 170: FPGA Receiver (structural) chip --
Page 171 and 172: FPGA Receiver (structural) chip IO_
Page 173 and 174: Number with an unused LUT 18 219 8%
Page 175 and 176: IO Utilization: Number of IOs: 26 N
Page 177 and 178: The Slice Logic Distribution report
Page 179 and 180: Router effort level (-rl): Standard
Page 181 and 182: oming_clock | HOLD | 0.519ns| | 0|
Page 183 and 184: Part | xc5vlx50tff1136-3 | Process
Page 185 and 186: Selected Device: 5vlx50tff1136-3 Sl
Page 187: used in combination with MAP -timin
Page 191 and 192: “For these implantable devices to
Page 193 and 194: microstimulator with a 1:4 demultip
Page 195 and 196: “Medical experiments have estimat
Page 197 and 198: A Retinomorphic Vision System “In
Page 199 and 200: “The common language of neuromorp
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