Retinal Prosthesis Dissertation - Student Home Pages
Retinal Prosthesis Dissertation - Student Home Pages
Retinal Prosthesis Dissertation - Student Home Pages
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pixel must equate to 0.02/1024 i.e. 0.00001953125s = 19531.25ns as shown in table<br />
5.<br />
Example Hierarchy<br />
T periodic (ns) T periodic (s) frequency (HZ) frequency (MHz)<br />
[1] Circa 25MHz 40 0.00000004 25000000 25 partial_spike<br />
[2] Circa 6.25MHz 160 0.00000016 6250000 6.25 spike<br />
[3] Circa 1.25MHz 800 0.0000008 1250000 1.25 outer_ pulse<br />
[4] Circa 25.6KHz 39062.5 3.9063E-05 25600 0.0256 pixel<br />
2nd Example<br />
Hierarchy<br />
[1] Circa 25000MHz 0.04 4E-11 25000000000 25000 partial_spike<br />
[2] Circa 6250MHz 0.16 1.6E-10 6250000000 6250 spike<br />
[3] Circa 1250MHz 0.8 8E-10 1250000000 1250 outer_ pulse<br />
[4] Circa 25MHz 40 0.00000004 25000000 25 pixel<br />
3rd Example<br />
Hierarchy<br />
[1]Circa 100MHz 10 0.00000001 100000000 100 partial_spike<br />
[2]Circa 25MHz 40 0.00000004 25000000 25 spike<br />
[3]Circa 5MHz 200 0.0000002 5000000 5 outer_ pulse<br />
[4]Circa 102.4KHz 9765.625 9.7656E-06 102400 0.1024 pixel<br />
Table 7 examples of clocking hierarchy<br />
The diagrams illustrate the component parts for construction of the sender chip. The<br />
first following top level block diagram illustrates the component parts for<br />
construction of the sender chip in high level programming terms and the second in<br />
Xilinx FPGA conceptual terms and thirdly in<br />
a VHDL programming<br />
description[Appendix C].
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