Retinal Prosthesis Dissertation - Student Home Pages

FPGA Receiver (structural) chip
blue_3: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "blue_wire_3"
blue_4: out STD_LOGIC_VECTOR (49 downto 0)--feeds to "blue_wire_4"
);
END COMPONENT; --produce_bit_wire_outputs
COMPONENT AER_test_stream_to_pulse_count is
--feeds "file_support_intense_pulses.vhd" & hence "intense_pulses.dat
generic (bit_width: integer: = 11); --Initially six, then altered to eleven.
Port ( ts_clock: in STD_LOGIC;
AER_RGB_incoming_stream:
in
STD_LOGIC_VECTOR (155 downto 0);
stream_red_pulse_count: out std_logic_vector (0
downto 0);
stream_green_pulse_count: out std_logic_vector (0
downto 0);
stream_blue_pulse_count: out std_logic_vector (0
downto 0);
out_red_counter: out integer;
out_green_counter: out integer;
out_blue_pulse_counter: out integer
);
END COMPONENT;
COMPONENT mapping_to_outgoing_addresses is
Port (implant_clk: in STD_LOGIC; --pixel clock
red_in: in STD_LOGIC_VECTOR (55 downto 0);
green_in: in STD_LOGIC_VECTOR (55 downto 0);
blue_in: in STD_LOGIC_VECTOR (55 downto 0);
red_outgoing_address_stream: in STD_LOGIC_VECTOR (5
downto 0);
green_outgoing_address_stream: in STD_LOGIC_VECTOR
(5 downto 0);
blue_outgoing_address_stream: in STD_LOGIC_VECTOR
(5 downto 0);
red_implant: out STD_LOGIC_VECTOR (55 downto 0);
green_implant: out STD_LOGIC_VECTOR (55 downto 0);
blue_implant: out STD_LOGIC_VECTOR (55 downto 0));
END COMPONENT;
COMPONENT generate_outgoing_address_streams is
--feeds "file_support_AER_outgoing_addresses.vhd" & hence
"outgoing_addresses.dat"
Port ( out_clock: in STD_LOGIC; --spike_clock
red_out_address: out std_logic_vector (5 downto 0);
green_out_address: out std_logic_vector (5 downto 0);
blue_out_address: out std_logic_vector (5 downto 0)
);
END COMPONENT;
COMPONENT file_support_AER_outgoing_addresses is
port (clk: in std_logic; --Sim_clock
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