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FPGA Receiver (structural) chip
--Appendix D FPGA Receiver chip
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
-- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--Replacing 146 occurrences of (19 downto 0) with (3 downto 0)!
--"short_AER_RGB_stream"
use IEEE.numeric_std.ALL; --to_signed is used with this library
entity top_wrapper is
Port (USER_CLK: in STD_LOGIC;
IO_L13P_11: out STD_LOGIC_VECTOR (3 downto 0);--"L33"(1) [1]
IO_L13N_11: out STD_LOGIC_VECTOR (3 downto 0);--"M32"(2) [2]
IO_L14P_11: out STD_LOGIC_VECTOR (3 downto 0);--"P34"(3) [3]
IO_L13P_12: out STD_LOGIC_VECTOR (3 downto 0);--"H5"(1) [4]
IO_L13N_12: out STD_LOGIC_VECTOR (3 downto 0);--"G5"(2) [5]
IO_L14P_12: out STD_LOGIC_VECTOR (3 downto 0);--"R11"(3) [6]
IO_L15P_12: out STD_LOGIC_VECTOR (3 downto 0);--"F5"(4) [7]
IO_L15N_12: out STD_LOGIC_VECTOR (3 downto 0);--"F6"(5) [8]
IO_L16P_12: out STD_LOGIC_VECTOR (3 downto 0);--"T10"(6) [9]
IO_L16N_12: out STD_LOGIC_VECTOR (3 downto 0);--"T11"(7) [10]
IO_L17P_12: out STD_LOGIC_VECTOR (3 downto 0);--"G6"(8) [11]
IO_L17N_12: out STD_LOGIC_VECTOR (3 downto 0);--"G7"(9) [12]
IO_L18P_12: out STD_LOGIC_VECTOR (3 downto 0);--"T9"(10) [13]
IO_L18N_12: out STD_LOGIC_VECTOR (3 downto 0);--"U10"(11) [14]
IO_L19P_12: out STD_LOGIC_VECTOR (3 downto 0);--"E6"(12) [15]
IO_L19N_12: out STD_LOGIC_VECTOR (3 downto 0);--"E7"(13) [16]
IO_L13P_13: out STD_LOGIC_VECTOR (3 downto 0);--“AK34” (1) [17]
IO_L13N_13: out STD_LOGIC_VECTOR (3 downto 0);--“AK33” (2) [18]
IO_L14P_13: out STD_LOGIC_VECTOR (3 downto 0);--“AG32” (3) [19]
IO_L15P_13: out STD_LOGIC_VECTOR (3 downto 0);--“AJ32” (4) [20]
IO_L15N_13: out STD_LOGIC_VECTOR (3 downto 0);--“AK32” (5) [21]
IO_L16P_13: out STD_LOGIC_VECTOR (3 downto 0);--“AL34” (6) [22]
IO_L16N_13: out STD_LOGIC_VECTOR (3 downto 0);--“AL33” (7) [23]
IO_L17P_13: out STD_LOGIC_VECTOR (3 downto 0);--“AM33” (8) [24]
IO_L17N_13: out STD_LOGIC_VECTOR (3 downto 0);--“AM32” (9) [25]
IO_L18P_13: out STD_LOGIC_VECTOR (3 downto 0);--“AN34” (10) [26]
IO_L18N_13: out STD_LOGIC_VECTOR (3 downto 0);--“AN33” (11) [27]
IO_L19P_13: out STD_LOGIC_VECTOR (3 downto 0);--“AN32” (12) [28]
IO_L19N_13: out STD_LOGIC_VECTOR (3 downto 0);--“AP32” (13) [29]
IO_L13P_15: out STD_LOGIC_VECTOR (3 downto 0);--“T31” (1) [30]
IO_L13N_15: out STD_LOGIC_VECTOR (3 downto 0);--“R31” (2) [31]
IO_L14P_15: out STD_LOGIC_VECTOR (3 downto 0);--“U30” (3) [32]
IO_L15P_15: out STD_LOGIC_VECTOR (3 downto 0);--“T28” (4) [33]
IO_L15N_15: out STD_LOGIC_VECTOR (3 downto 0);--“T29” (5) [34]
IO_L16P_15: out STD_LOGIC_VECTOR (3 downto 0);--“U27” (6) [35]
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