Retinal Prosthesis Dissertation - Student Home Pages

FPGA Receiver (structural) chip
--signal red_wire_1: std_logic_vector (999 downto 0);
--signal red_wire_2: std_logic_vector (999 downto 0);
--signal red_wire_3: std_logic_vector (999 downto 0);
--signal red_wire_4: std_logic_vector (999 downto 0);
--signal green_wire_1: std_logic_vector (999 downto 0);
--signal green_wire_2: std_logic_vector (999 downto 0);
--signal green_wire_3: std_logic_vector (999 downto 0);
--signal green_wire_4: std_logic_vector (999 downto 0);
--signal blue_wire_1: std_logic_vector (999 downto 0);
--signal blue_wire_2: std_logic_vector (999 downto 0);
--signal blue_wire_3: std_logic_vector (999 downto 0);
--signal blue_wire_4: std_logic_vector (999 downto 0);
--signal red_wire_1: std_logic_vector (199 downto 0);
--signal red_wire_2: std_logic_vector (199 downto 0);
--signal red_wire_3: std_logic_vector (199 downto 0);
--signal red_wire_4: std_logic_vector (199 downto 0);
--signal green_wire_1: std_logic_vector (199 downto 0);
--signal green_wire_2: std_logic_vector (199 downto 0);
--signal green_wire_3: std_logic_vector (199 downto 0);
--signal green_wire_4: std_logic_vector (199 downto 0);
--signal blue_wire_1: std_logic_vector (199 downto 0);
--signal blue_wire_2: std_logic_vector (199 downto 0);
--signal blue_wire_3: std_logic_vector (199 downto 0);
--signal blue_wire_4: std_logic_vector (199 downto 0);
--signal red_wire_1: std_logic_vector (3 downto 0);
--signal red_wire_2: std_logic_vector (3 downto 0);
--signal red_wire_3: std_logic_vector (3 downto 0);
--signal red_wire_4: std_logic_vector (3 downto 0);
--signal green_wire_1: std_logic_vector (3 downto 0);
--signal green_wire_2: std_logic_vector (3 downto 0);
--signal green_wire_3: std_logic_vector (3 downto 0);
--signal green_wire_4: std_logic_vector (3 downto 0);
--signal blue_wire_1: std_logic_vector (3 downto 0);
--signal blue_wire_2: std_logic_vector (3 downto 0);
--signal blue_wire_3: std_logic_vector (3 downto 0);
--signal blue_wire_4: std_logic_vector (3 downto 0);
signal red_wire_1: std_logic_vector (3 downto 0);
signal red_wire_2: std_logic_vector (3 downto 0);
signal red_wire_3: std_logic_vector (3 downto 0);
signal red_wire_4: std_logic_vector (3 downto 0);
signal red_wire_5: std_logic_vector (3 downto 0);
signal red_wire_6: std_logic_vector (3 downto 0);
signal red_wire_7: std_logic_vector (3 downto 0);
signal red_wire_8: std_logic_vector (3 downto 0);
signal red_wire_9: std_logic_vector (3 downto 0);
signal red_wire_10: std_logic_vector (3 downto 0);
signal red_wire_11: std_logic_vector (3 downto 0);
signal red_wire_12: std_logic_vector (3 downto 0);
signal red_wire_13: std_logic_vector (3 downto 0);
signal red_wire_14: std_logic_vector (3 downto 0);
signal red_wire_15: std_logic_vector (3 downto 0);
164 of 200