Retinal Prosthesis Dissertation - Student Home Pages

FPGA Receiver (structural) chip
IO_L16N_15: out STD_LOGIC_VECTOR (3 downto 0);--“U28” (7) [36]
IO_L17P_15: out STD_LOGIC_VECTOR (3 downto 0);--“R26” (8) [37]
IO_L17N_15: out STD_LOGIC_VECTOR (3 downto 0);--“R27” (9) [38]
IO_L18P_15: out STD_LOGIC_VECTOR (3 downto 0);--“U26” (10) [39]
IO_L18N_15: out STD_LOGIC_VECTOR (3 downto 0);--“T26” (11) [40]
IO_L19P_15: out STD_LOGIC_VECTOR (3 downto 0);--“U25” (12) [41]
IO_L19N_15: out STD_LOGIC_VECTOR (3 downto 0);--“T25” (13) [42]
IO_L13P_17: out STD_LOGIC_VECTOR (3 downto 0);--“AD30” (1) [43]
IO_L13N_17: out STD_LOGIC_VECTOR (3 downto 0);--"AC29}"(2) [44]
IO_L14P_17: out STD_LOGIC_VECTOR (3 downto 0);--"AF31"(3) [45]
IO_L15P_17: out STD_LOGIC_VECTOR (3 downto 0);--"AE29"(4) [46]
IO_L15N_17: out STD_LOGIC_VECTOR (3 downto 0);--"AD29"(5) [47]
IO_L16P_17: out STD_LOGIC_VECTOR (3 downto 0)--"AJ31"(6) [48]
--IO_L13P_18: out STD_LOGIC_VECTOR (999 downto 0);--"Y11" {1}
--IO_L13P_19: out STD_LOGIC_VECTOR (999 downto 0);--"K28" [215]
--IO_L13N_19: out STD_LOGIC_VECTOR (999 downto 0);--"L28" {3}
--IO_L14P_19: out STD_LOGIC_VECTOR (999 downto 0);--"K27" [215]
--IO_L15P_19: out STD_LOGIC_VECTOR (999 downto 0);--"M28" [215]
--IO_L17P_20: out STD_LOGIC_VECTOR (999 downto 0);--"E12" {6}
--IO_L17N_20: out STD_LOGIC_VECTOR (999 downto 0);--"E13" {7}
--IO_L18P_20: out STD_LOGIC_VECTOR (999 downto 0);--"N10" {8}
--IO_L18N_20: out STD_LOGIC_VECTOR (999 downto 0); --"N9" {9}
--IO_L19P_20: out STD_LOGIC_VECTOR (999 downto 0);--"F13" {10}
--IO_L19N_20: out STD_LOGIC_VECTOR (999 downto 0);--"G13" {11}
--IO_L13P_21: out STD_LOGIC_VECTOR (999 downto 0);--"AF24" {12}
--IO_L13N_21: out STD_LOGIC_VECTOR (999 downto 0);--"AG25" {13}
--IO_L14P_21: out STD_LOGIC_VECTOR (999 downto 0);--"AG27" {14}
--IO_L15P_21: out STD_LOGIC_VECTOR (999 downto 0);--"AF25" {15}
--IO_L15N_21: out STD_LOGIC_VECTOR (999 downto 0);--"AF26" {16}
--IO_L16P_21: out STD_LOGIC_VECTOR (999 downto 0);--"AE27" {17}
--IO_L16N_21: out STD_LOGIC_VECTOR (999 downto 0);--"AE26" {18}
--IO_L17P_21: out STD_LOGIC_VECTOR (999 downto 0);--"AC25" {19}
--IO_L17N_21: out STD_LOGIC_VECTOR (999 downto 0);--"AC24" {20}
--IO_L18P_21: out STD_LOGIC_VECTOR (999 downto 0);--"AD26" {21}
);
end top_wrapper;
--1024 x 3 = 3072 i.e. three planes describing a 64 pixelcount picture
--As a pixel consists of three planes, 150 potential pulses are required per pixel
--That is 50 potential pulses per plane per pixel
architecture Behavioral of top_wrapper is
--type current integer range -70 uA to +70 uA
-- units
-- uA;
-- mA = 1000uA;
-- end units;
--COMPONENT mem_of_256_short_aer_stream is
----generic (width: integer; addr_width: integer);
-- Port (clka: in STD_LOGIC;
-- addra: in STD_LOGIC_VECTOR (7 downto 0);
-- douta: out STD_LOGIC_VECTOR (25 downto 0));
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