Retinal Prosthesis Dissertation - Student Home Pages

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5.8 Stimulator <strong>Retinal</strong> Interface In the sub_retinal approach the electrode array is positioned, replacing damaged photoreceptors, such that the electrodes impinge into the INL and stimulate bipolar cells. In the epiretinal approach the electrode array is tacked onto the innermost layer of the retina and the electrodes stimulate the axons or soma of the ganglion cells; the stimulator circuitry is atop of the electrode array. The distinctions between these two approaches were being formed in the 1990’s when several major projects in the USA, Germany and elsewhere were on-going. Early electrode array formulations [120, 206] were housed on thin flexible polyimide strips; e.g. 4µm thick, on which at one end was housed the stimulator circuitry and at the other the electrodes to be held to the retina (≈250µm thick). In 1999 [207] Humayun et al, in their investigation of planar disc electrodes of > 125µm noted a dramatic increase in current requirement, when the distance between a stimulating electrode and the retina was more than 0.5mm (500µm); thus highlighting the importance of this particular parameter. 5.8.1 Factors affecting current requirement for stimulation Electrode positioning; in terms of distance [52] from electrode to point of stimulation e.g. 30µm [49] , electrode geometry; in terms of size and shape, electrode material in terms of biocompatibility and charge delivery capability. Electrode arrays will also take into consideration number of electrodes, electrode spacing and number of electrodes actually to be or being used. In the case of a sub_retinal array [122, 174] typically the number of electrodes will match up to the number of photodiodes as each photodiode will be connected to the electrode designed ostensibly to stimulate bipolar cells. In the case of an epiretinal array it was realised a decade ago (2002) [174] that to achieve safe current density with smaller electrodes it would be necessary to use penetrating electrodes rather than planar electrodes; as this geometry would allow a reduced distance to target cells that are embedded in ganglion cell layers of 20-40µm within nerve fibre layers of 20-200µm. Electrode materials used for stimulation are titanium nitride, platinum, and iridium oxide [208], which have good charge carrying capacity. 103 of 200
5.8.2 Electrode size and positioning in current retinal approaches The diameter of implanted electrodes in current retinal approaches [88, 103, 209, 210] previous to 2007 has been of an order of magnitude of > 50µm. During 2007 it was determined that a change in electrode-retina distance of 100µm can result in a ten times change in threshold stimulation and also early results in the Second Sight device (epiretinal) in Humans showed an inverse square relationship between impedance and retina-electrode distance [210]. Clinical trials also began on the Second Sight Second-Generation implant at this time (www.2-sight.com) an earlier (2006) subretinal device [115] by Retina Implant GmbH and an a second clinical trial of an epiretinal device by Intelligent Medical Implants AG. In this reference it was pointed out that as an individual with 20/20 vision can resolve differences of 1/60 of one degree of visual angle that this would translate to 5µm on the retina implying that 5µm electrodes would be needed for vision at this level. An estimate was also that a 100µm electrode could provide vision equivalent to 20/400 acuity. In 2008 [176] the EPI-RET-3 prosthesis subsequently had 3D-electrodes with a diameter of 100µm and a height of 25µm. 5.8.3 Recent developments 2010 to now (2012) has seen a resurgence of work in this area; subretinally [23] the use of a parylene-based 3-D microelectrode array (MEA) demonstrated in vitro and in vivo how distance between the stimulating electrode (Ti/Au/Pt) and targeted cells could be decreased by the use of the tip shaped electrodes as opposed to nearly flat planar electrodes. Epiretinally [102] an in vivo study indicates smaller current thresholds; ≈100µA than previous thresholds; 500µA. Also [97] the possibility of lower stimulus voltage for 3-D electrodes as opposed to flat planar electrodes. The latest penetrating array for epiretinal prosthesis [29] makes possible high density arrays (≈100 electrodes/mm 2 ) and arrays of 2µm, 5µm, 10µm, 20µm and 30µm diameter with heights of 60µm-100µm and pitches of 50µm-400µm. 104 of 200
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
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1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
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Adaptive linear combiner w 0 1 Let
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is correct (one class) and -1 (the
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x2 Linear separation 1.00 0.90 0.80
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This is also the Cartesian co-ordin
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2.4 Comparison to Frame Based Repre
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Typical GOP structure (Typically an
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point is an event occurs for spike
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2.5.1 Files in Appendix A “ycut.m
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MPEG-2 setup AER setup Camera Camer
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2.6.2 FPGA representation of epi_re
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Chapter 3 Concepts An epiretinal im
Page 53 and 54: AER Transmission lines INPUT image
Page 55 and 56: electrical pulse generated is calle
Page 57 and 58: Figure 25 Retinal colour processing
Page 59 and 60: cells to modulate this luminance pa
Page 61 and 62: L+ M- + - R-G G-R B-Y Y-B Note: L(r
Page 63 and 64: 3.6.2 Retinal operations Light reac
Page 65 and 66: quantified by number of cycles pres
Page 67 and 68: (Where * is the convolution operato
Page 69 and 70: T frame C * R * M p Tpacket i.e. Tp
Page 71 and 72: e relaxed and from (2) the temporal
Page 73 and 74: one tw o three four five six seven
Page 75 and 76: 3.8.1 Other test images For other b
Page 77 and 78: Tspike (4ms) Ispike (16ms: interspi
Page 79 and 80: INDIGO ORANGE YELLOW MAGENTA CYAN B
Page 81 and 82: 4.1 Sender concepts From chapter on
Page 83 and 84: pixel must equate to 0.02/1024 i.e.
Page 85 and 86: Clocking hierarchy (32 by 32 image)
Page 87 and 88: the number of address bits will alt
Page 89 and 90: Translation report, (3) Map report,
Page 91 and 92: 90 of 200 CLKIN_IN RST_IN pixelcloc
Page 93 and 94: incorporate colour planes for each
Page 95 and 96: Chapter 5 Receiver chip The followi
Page 97 and 98: 5.2 Power Analysis Xilinx FPGAs hav
Page 99 and 100: 98 of 200 produce_wire _outputs Ins
Page 101 and 102: 5.5.1 Incoming (short) AER stream T
Page 103: Receiver Red plane r1 DAC (4-bit) T
Page 107 and 108: sequence of wiring from the receive
Page 109 and 110: does this is to inject an equivalen
Page 111 and 112: 6.2.2 Envisaged retinal array This
Page 113 and 114: a monochrome camera in this space i
Page 115 and 116: 632mW) thus extending battery life
Page 117 and 118: For the implemented/structural case
Page 119 and 120: The sender and receiver circuitry p
Page 121 and 122: Bibliography 1. Woodburn R. Murray
Page 123 and 124: 38. Banks, D.J., P. Degenaar, and C
Page 125 and 126: 74. Freeman, J.A., Skapura, D. M.,
Page 127 and 128: 109. Weiland, J.D., et al. Progress
Page 129 and 130: 141. Indiveri G. Chicca E. Douglas
Page 131 and 132: 172. Singh, P.R., et al. A matched
Page 133 and 134: 206. Stieglitz, T., et al. Developm
Page 135 and 136: xmixedsource; numberOfFrames = 8; f
Page 137 and 138: %check {k} =imread (['D:\abc\subima
Page 139 and 140: %Two for loops the first (outer loo
Page 141 and 142: %Row break rr6c1=000; rr6c2=000; rr
Page 143 and 144: --Appendix B FPGA Test setup librar
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Page 147 and 148: DVI_XCLK_P clock_25MHz, spike_cloc
Page 149 and 150: use IEEE.STD_LOGIC_UNSIGNED.ALL; --
Page 151 and 152: --Appendix C FPGA Sender chip libra
Page 153 and 154: -- else -- resit '1', CLKDV_OUT =>
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FPGA Receiver (structural) chip --A
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FPGA Receiver (structural) chip --E
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FPGA Receiver (structural) chip --r
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FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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