Retinal Prosthesis Dissertation - Student Home Pages

FPGA Receiver (structural) chip
signal red_wire_16: std_logic_vector (3 downto 0);
signal green_wire_1: std_logic_vector (3 downto 0);
signal green_wire_2: std_logic_vector (3 downto 0);
signal green_wire_3: std_logic_vector (3 downto 0);
signal green_wire_4: std_logic_vector (3 downto 0);
signal green_wire_5: std_logic_vector (3 downto 0);
signal green_wire_6: std_logic_vector (3 downto 0);
signal green_wire_7: std_logic_vector (3 downto 0);
signal green_wire_8: std_logic_vector (3 downto 0);
signal green_wire_9: std_logic_vector (3 downto 0);
signal green_wire_10: std_logic_vector (3 downto 0);
signal green_wire_11: std_logic_vector (3 downto 0);
signal green_wire_12: std_logic_vector (3 downto 0);
signal green_wire_13: std_logic_vector (3 downto 0);
signal green_wire_14: std_logic_vector (3 downto 0);
signal green_wire_15: std_logic_vector (3 downto 0);
signal green_wire_16: std_logic_vector (3 downto 0);
signal blue_wire_1: std_logic_vector (3 downto 0);
signal blue_wire_2: std_logic_vector (3 downto 0);
signal blue_wire_3: std_logic_vector (3 downto 0);
signal blue_wire_4: std_logic_vector (3 downto 0);
signal blue_wire_5: std_logic_vector (3 downto 0);
signal blue_wire_6: std_logic_vector (3 downto 0);
signal blue_wire_7: std_logic_vector (3 downto 0);
signal blue_wire_8: std_logic_vector (3 downto 0);
signal blue_wire_9: std_logic_vector (3 downto 0);
signal blue_wire_10: std_logic_vector (3 downto 0);
signal blue_wire_11: std_logic_vector (3 downto 0);
signal blue_wire_12: std_logic_vector (3 downto 0);
signal blue_wire_13: std_logic_vector (3 downto 0);
signal blue_wire_14: std_logic_vector (3 downto 0);
signal blue_wire_15: std_logic_vector (3 downto 0);
signal blue_wire_16: std_logic_vector (3 downto 0);
begin
--tb_clk: process is
--begin
-- incoming_clock