Retinal Prosthesis Dissertation - Student Home Pages

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FPGA Receiver (structural) chip blue_8: out STD_LOGIC_VECTOR (3 downto 0);--feeds to "blue_wire_8" blue_9: out STD_LOGIC_VECTOR (3 downto 0);--feeds to "blue_wire_9" blue_10: out STD_LOGIC_VECTOR (3 downto 0);--feeds to "blue_wire_10" blue_11: out STD_LOGIC_VECTOR (3 downto 0);--feeds to "blue_wire_11" blue_12: out STD_LOGIC_VECTOR (3 downto 0);--feeds to "blue_wire_12" blue_13: out STD_LOGIC_VECTOR (3 downto 0);--feeds to "blue_wire_13" blue_14: out STD_LOGIC_VECTOR (3 downto 0);--feeds to "blue_wire_14" blue_15: out STD_LOGIC_VECTOR (3 downto 0);--feeds to "blue_wire_15" blue_16: out STD_LOGIC_VECTOR (3 downto 0)--feeds to "blue_wire_16" ); END COMPONENT; --produce_wire_outputs COMPONENT produce_fast_wire_outputs is Port (wire_clock: in STD_LOGIC; red: in STD_LOGIC_VECTOR (199 downto 0);--from "outer_red_pulse_stream" green: in STD_LOGIC_VECTOR (199 downto 0);--from "outer_green_pulse_stream" blue: in STD_LOGIC_VECTOR (199 downto 0);--from "outer_blue_pulse_stream" red_1: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "red_wire_1" red_2: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "red_wire_2" red_3: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "red_wire_3" red_4: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "red_wire_4" green_1: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "green_wire_1" green_2: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "green_wire_2" green_3: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "green_wire_3" green_4: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "green_wire_4" blue_1: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "blue_wire_1" blue_2: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "blue_wire_2" blue_3: out STD_LOGIC_VECTOR (199 downto 0);--feeds to "blue_wire_3" blue_4: out STD_LOGIC_VECTOR (199 downto 0)--feeds to "blue_wire_4" ); END COMPONENT; --produce_fast_wire_outputs COMPONENT produce_bit_wire_outputs is Port (wire_clock: in STD_LOGIC; red: in STD_LOGIC_VECTOR (49 downto 0);--from "outer_red_pulse_stream" green: in STD_LOGIC_VECTOR (49 downto 0);--from "outer_green_pulse_stream" blue: in STD_LOGIC_VECTOR (49 downto 0);--from "outer_blue_pulse_stream" red_1: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "red_wire_1" red_2: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "red_wire_2" red_3: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "red_wire_3" red_4: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "red_wire_4" green_1: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "green_wire_1" green_2: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "green_wire_2" green_3: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "green_wire_3" green_4: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "green_wire_4" blue_1: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "blue_wire_1" blue_2: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "blue_wire_2" 159 of 200
FPGA Receiver (structural) chip blue_3: out STD_LOGIC_VECTOR (49 downto 0);--feeds to "blue_wire_3" blue_4: out STD_LOGIC_VECTOR (49 downto 0)--feeds to "blue_wire_4" ); END COMPONENT; --produce_bit_wire_outputs COMPONENT AER_test_stream_to_pulse_count is --feeds "file_support_intense_pulses.vhd" & hence "intense_pulses.dat generic (bit_width: integer: = 11); --Initially six, then altered to eleven. Port ( ts_clock: in STD_LOGIC; AER_RGB_incoming_stream: in STD_LOGIC_VECTOR (155 downto 0); stream_red_pulse_count: out std_logic_vector (0 downto 0); stream_green_pulse_count: out std_logic_vector (0 downto 0); stream_blue_pulse_count: out std_logic_vector (0 downto 0); out_red_counter: out integer; out_green_counter: out integer; out_blue_pulse_counter: out integer ); END COMPONENT; COMPONENT mapping_to_outgoing_addresses is Port (implant_clk: in STD_LOGIC; --pixel clock red_in: in STD_LOGIC_VECTOR (55 downto 0); green_in: in STD_LOGIC_VECTOR (55 downto 0); blue_in: in STD_LOGIC_VECTOR (55 downto 0); red_outgoing_address_stream: in STD_LOGIC_VECTOR (5 downto 0); green_outgoing_address_stream: in STD_LOGIC_VECTOR (5 downto 0); blue_outgoing_address_stream: in STD_LOGIC_VECTOR (5 downto 0); red_implant: out STD_LOGIC_VECTOR (55 downto 0); green_implant: out STD_LOGIC_VECTOR (55 downto 0); blue_implant: out STD_LOGIC_VECTOR (55 downto 0)); END COMPONENT; COMPONENT generate_outgoing_address_streams is --feeds "file_support_AER_outgoing_addresses.vhd" & hence "outgoing_addresses.dat" Port ( out_clock: in STD_LOGIC; --spike_clock red_out_address: out std_logic_vector (5 downto 0); green_out_address: out std_logic_vector (5 downto 0); blue_out_address: out std_logic_vector (5 downto 0) ); END COMPONENT; COMPONENT file_support_AER_outgoing_addresses is port (clk: in std_logic; --Sim_clock 160 of 200
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
Page 9 and 10:
Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
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1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
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Adaptive linear combiner w 0 1 Let
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is correct (one class) and -1 (the
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x2 Linear separation 1.00 0.90 0.80
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This is also the Cartesian co-ordin
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2.4 Comparison to Frame Based Repre
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Typical GOP structure (Typically an
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point is an event occurs for spike
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2.5.1 Files in Appendix A “ycut.m
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MPEG-2 setup AER setup Camera Camer
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2.6.2 FPGA representation of epi_re
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Chapter 3 Concepts An epiretinal im
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AER Transmission lines INPUT image
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electrical pulse generated is calle
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Figure 25 Retinal colour processing
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cells to modulate this luminance pa
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L+ M- + - R-G G-R B-Y Y-B Note: L(r
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3.6.2 Retinal operations Light reac
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quantified by number of cycles pres
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(Where * is the convolution operato
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T frame C * R * M p Tpacket i.e. Tp
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e relaxed and from (2) the temporal
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one tw o three four five six seven
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3.8.1 Other test images For other b
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Tspike (4ms) Ispike (16ms: interspi
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INDIGO ORANGE YELLOW MAGENTA CYAN B
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4.1 Sender concepts From chapter on
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pixel must equate to 0.02/1024 i.e.
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Clocking hierarchy (32 by 32 image)
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the number of address bits will alt
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Translation report, (3) Map report,
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90 of 200 CLKIN_IN RST_IN pixelcloc
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incorporate colour planes for each
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Chapter 5 Receiver chip The followi
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5.2 Power Analysis Xilinx FPGAs hav
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98 of 200 produce_wire _outputs Ins
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5.5.1 Incoming (short) AER stream T
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Receiver Red plane r1 DAC (4-bit) T
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5.8.2 Electrode size and positionin
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sequence of wiring from the receive
Page 109 and 110: does this is to inject an equivalen
Page 111 and 112: 6.2.2 Envisaged retinal array This
Page 113 and 114: a monochrome camera in this space i
Page 115 and 116: 632mW) thus extending battery life
Page 117 and 118: For the implemented/structural case
Page 119 and 120: The sender and receiver circuitry p
Page 121 and 122: Bibliography 1. Woodburn R. Murray
Page 123 and 124: 38. Banks, D.J., P. Degenaar, and C
Page 125 and 126: 74. Freeman, J.A., Skapura, D. M.,
Page 127 and 128: 109. Weiland, J.D., et al. Progress
Page 129 and 130: 141. Indiveri G. Chicca E. Douglas
Page 131 and 132: 172. Singh, P.R., et al. A matched
Page 133 and 134: 206. Stieglitz, T., et al. Developm
Page 135 and 136: xmixedsource; numberOfFrames = 8; f
Page 137 and 138: %check {k} =imread (['D:\abc\subima
Page 139 and 140: %Two for loops the first (outer loo
Page 141 and 142: %Row break rr6c1=000; rr6c2=000; rr
Page 143 and 144: --Appendix B FPGA Test setup librar
Page 145 and 146: stream_blue_pulse_count: out std_lo
Page 147 and 148: DVI_XCLK_P clock_25MHz, spike_cloc
Page 149 and 150: use IEEE.STD_LOGIC_UNSIGNED.ALL; --
Page 151 and 152: --Appendix C FPGA Sender chip libra
Page 153 and 154: -- else -- resit '1', CLKDV_OUT =>
Page 155 and 156: FPGA Receiver (structural) chip --A
Page 157 and 158: FPGA Receiver (structural) chip --E
Page 159: FPGA Receiver (structural) chip --r
Page 163 and 164: FPGA Receiver (structural) chip con
Page 165 and 166: FPGA Receiver (structural) chip --s
Page 167 and 168: FPGA Receiver (structural) chip --
Page 169 and 170: FPGA Receiver (structural) chip --
Page 171 and 172: FPGA Receiver (structural) chip IO_
Page 173 and 174: Number with an unused LUT 18 219 8%
Page 175 and 176: IO Utilization: Number of IOs: 26 N
Page 177 and 178: The Slice Logic Distribution report
Page 179 and 180: Router effort level (-rl): Standard
Page 181 and 182: oming_clock | HOLD | 0.519ns| | 0|
Page 183 and 184: Part | xc5vlx50tff1136-3 | Process
Page 185 and 186: Selected Device: 5vlx50tff1136-3 Sl
Page 187 and 188: used in combination with MAP -timin
Page 189 and 190: Data Sheet report: ----------------
Page 191 and 192: “For these implantable devices to
Page 193 and 194: microstimulator with a 1:4 demultip
Page 195 and 196: “Medical experiments have estimat
Page 197 and 198: A Retinomorphic Vision System “In
Page 199 and 200: “The common language of neuromorp
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