Retinal Prosthesis Dissertation - Student Home Pages

use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvimux is
Port (dvi_clk: IN STD_LOGIC;
r_out: in STD_LOGIC_VECTOR (7 downto 0);
g_out: in STD_LOGIC_VECTOR (7 downto 0);
b_out: in STD_LOGIC_VECTOR (7 downto 0);
--TFT_DVI_DATA: out STD_LOGIC_VECTOR (11
downto 0)
TFT_DVI_DATA_0: out std_logic;
TFT_DVI_DATA_1: out std_logic;
TFT_DVI_DATA_2: out std_logic;
TFT_DVI_DATA_3: out std_logic;
TFT_DVI_DATA_4: out std_logic;
TFT_DVI_DATA_5: out std_logic;
TFT_DVI_DATA_6: out std_logic;
TFT_DVI_DATA_7: out std_logic;
TFT_DVI_DATA_8: out std_logic;
TFT_DVI_DATA_9: out std_logic;
TFT_DVI_DATA_10: out std_logic;
TFT_DVI_DATA_11: out std_logic
);
end dvimux;
architecture Behavioral of dvimux is
begin
produce_12_bit_word_twice: process (dvi_clk, r_out, g_out, b_out)
variable TFT_DVI_DATA: std_logic_vector (11 downto 0);
begin
if dvi_clk = '1' then
--if (dvi_clk'event) AND (dvi_clk = '1') then
--if rising_edge (dvi_clk) then
--TFT_DVI_DATA:= r_out (7 downto 0) & g_out (7 downto 4);
TFT_DVI_DATA:= r_out (7 downto 6) & g_out (7 downto 6) & b_out (7 downto 6)
& r_out (5 downto 4) & g_out (5 downto 4) & b_out (5 downto 4);
--elsif (dvi_clk'event) AND (dvi_clk = '0') then
elsif dvi_clk = '0' then
--elsif falling_edge (dvi_clk) then --not supported in the current software release!
--TFT_DVI_DATA:= g_out (3 downto 0) & b_out (7 downto 0);
TFT_DVI_DATA:= r_out (3 downto 2) & g_out (3 downto 2) & b_out (3 downto 2)
& r_out (1 downto 0) & g_out (1 downto 0) & b_out (1 downto 0);
-- TFT_DVI_DATA_0