Retinal Prosthesis Dissertation - Student Home Pages

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In the Xilinx Virtex 5 the DCM has the following possible divisions from either 400MHz or 100MHz: 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 1`5 and 16. So one possible combination to obtain 400kHz as the `out_clock’ value would derive 40MHz as the output from the DCM and divide this by 100 in the programming block labeled “get_partial_clock_from_incoming_clock”. At 5fps for the same image to obtain 80kHz as the out_clock derive 20MHz as the output from the DCM and divide this by 250. In the block “get_spike_on_from_partial_spike_clock” divide by four to get the spike_clock frequency for all fps e.g. @25fps this would be100kHz. In the block get pixel_clock_from_partial_spike_clock divide by one thousand to get the pixel frequency for all fps e.g. @25fps this would be 400Hz The three instance of the “pulsar” block convert conventional 24 bit colour measure to a pulse count (described earlier), over time, for each of the three colour planes: red, green and blue. The counter counts and outputs the address bits for each pixel as it occurs. Finally “pulse_count_to_pc_stream” time multiplexes and outputs the AER stream consisting of AER packets with a payload of 18 bits. The first six bits of the payload represent the colour intensity for the red plane, followed by six bits for green and blue planes respectively. 4.6 Chapter summary The size of the image in pixel count (to be transmitted) will be limited by the number of electrodes possible at the retinal implant and presently (2010) this is expected to rise to over 1000 within several years. For the sender chip; programmes were completed both behaviourally and structurally i.e. synthesised and implemented for image sizes ranging from 16 pixels (4 by 4) up to 1024 pixels (32 by 32). To 91 of 200
incorporate colour planes for each pixel the electrode requirement, when received by the receiver chip, will increase for each of those image sizes; shown in Table 9. In essence the sender chip converts the colour image obtained from a commercial, off-the-shelf (COTS) camera to an AER stream. AER packet bit length will increase with image size as shown in the charts, following table 9 (source: aer_compare.xls). pix_count x 3 4 12 8 24 16 48 32 96 64 192 128 384 256 768 512 1536 1024 3072 Table 10 electrode requirement 1200 1000 800 600 400 Total bit length pixel count 200 0 20 22 24 26 28 Figure 44 upto 1024 image i.e. 32 by 32 92 of 200
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
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1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
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Adaptive linear combiner w 0 1 Let
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is correct (one class) and -1 (the
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x2 Linear separation 1.00 0.90 0.80
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This is also the Cartesian co-ordin
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2.4 Comparison to Frame Based Repre
Page 41 and 42: Typical GOP structure (Typically an
Page 43 and 44: point is an event occurs for spike
Page 45 and 46: 2.5.1 Files in Appendix A “ycut.m
Page 47 and 48: MPEG-2 setup AER setup Camera Camer
Page 49 and 50: 2.6.2 FPGA representation of epi_re
Page 51 and 52: Chapter 3 Concepts An epiretinal im
Page 53 and 54: AER Transmission lines INPUT image
Page 55 and 56: electrical pulse generated is calle
Page 57 and 58: Figure 25 Retinal colour processing
Page 59 and 60: cells to modulate this luminance pa
Page 61 and 62: L+ M- + - R-G G-R B-Y Y-B Note: L(r
Page 63 and 64: 3.6.2 Retinal operations Light reac
Page 65 and 66: quantified by number of cycles pres
Page 67 and 68: (Where * is the convolution operato
Page 69 and 70: T frame C * R * M p Tpacket i.e. Tp
Page 71 and 72: e relaxed and from (2) the temporal
Page 73 and 74: one tw o three four five six seven
Page 75 and 76: 3.8.1 Other test images For other b
Page 77 and 78: Tspike (4ms) Ispike (16ms: interspi
Page 79 and 80: INDIGO ORANGE YELLOW MAGENTA CYAN B
Page 81 and 82: 4.1 Sender concepts From chapter on
Page 83 and 84: pixel must equate to 0.02/1024 i.e.
Page 85 and 86: Clocking hierarchy (32 by 32 image)
Page 87 and 88: the number of address bits will alt
Page 89 and 90: Translation report, (3) Map report,
Page 91: 90 of 200 CLKIN_IN RST_IN pixelcloc
Page 95 and 96: Chapter 5 Receiver chip The followi
Page 97 and 98: 5.2 Power Analysis Xilinx FPGAs hav
Page 99 and 100: 98 of 200 produce_wire _outputs Ins
Page 101 and 102: 5.5.1 Incoming (short) AER stream T
Page 103 and 104: Receiver Red plane r1 DAC (4-bit) T
Page 105 and 106: 5.8.2 Electrode size and positionin
Page 107 and 108: sequence of wiring from the receive
Page 109 and 110: does this is to inject an equivalen
Page 111 and 112: 6.2.2 Envisaged retinal array This
Page 113 and 114: a monochrome camera in this space i
Page 115 and 116: 632mW) thus extending battery life
Page 117 and 118: For the implemented/structural case
Page 119 and 120: The sender and receiver circuitry p
Page 121 and 122: Bibliography 1. Woodburn R. Murray
Page 123 and 124: 38. Banks, D.J., P. Degenaar, and C
Page 125 and 126: 74. Freeman, J.A., Skapura, D. M.,
Page 127 and 128: 109. Weiland, J.D., et al. Progress
Page 129 and 130: 141. Indiveri G. Chicca E. Douglas
Page 131 and 132: 172. Singh, P.R., et al. A matched
Page 133 and 134: 206. Stieglitz, T., et al. Developm
Page 135 and 136: xmixedsource; numberOfFrames = 8; f
Page 137 and 138: %check {k} =imread (['D:\abc\subima
Page 139 and 140: %Two for loops the first (outer loo
Page 141 and 142: %Row break rr6c1=000; rr6c2=000; rr
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--Appendix B FPGA Test setup librar
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stream_blue_pulse_count: out std_lo
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DVI_XCLK_P clock_25MHz, spike_cloc
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use IEEE.STD_LOGIC_UNSIGNED.ALL; --
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--Appendix C FPGA Sender chip libra
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-- else -- resit '1', CLKDV_OUT =>
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FPGA Receiver (structural) chip --A
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FPGA Receiver (structural) chip --E
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FPGA Receiver (structural) chip --r
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FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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