Retinal Prosthesis Dissertation - Student Home Pages

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time for T partial_spike ; nominally the `quarter component of a biphasic pulse, is 156.25ns/4 = 39.0625ns (a thousandth of T packet ) giving a frequency of 25.6MHz. f packet T spike f spike (f biphasic ) fps T frame row col pix_count T packet (ns) (kHz) (T biphasic )(ns) (MHz) 25 0.04 32 32 1024 39062.5 25600 156.25 6.4 25 0.04 16 16 256 156250 6400 625 1.6 25 0.04 8 8 64 625000 1600 2500 0.4 25 0.04 4 4 16 2500000 400 10000 0.1 25 0.04 2 2 4 10000000 100 40000 0.025 50 0.02 32 32 1024 19531.25 51200 78.125 12.8 50 0.02 16 16 256 78125 12800 312.5 3.2 50 0.02 8 8 64 312500 3200 1250 0.8 50 0.02 4 4 16 1250000 800 5000 0.2 50 0.02 2 2 4 5000000 200 20000 0.05 100 0.01 32 32 1024 9765.625 102400 39.0625 25.6 100 0.01 16 16 256 39062.5 25600 156.25 6.4 100 0.01 8 8 64 156250 6400 625 1.6 100 0.01 4 4 16 625000 1600 2500 0.4 100 0.01 2 2 4 2500000 400 10000 0.1 Table 11 clocking calculations The following table (taken from “fps_calcs.xls”) illustrates these calculations: Circa 25MHz f f(kHz) f(MHz) T periodic T periodic(ns) T periodic(µ) T aer_stream 25 0.025 0.000025 0.04 40000000 40000 3.90625E- T pixel 25600 25.6 0.0256 05 39062.5 39.0625 T spike 6400000 6400 6.4 1.5625E-07 156.25 0.15625 3.90625E- T partial_spike circa 40ns 25600000 25600 25.6 08 39.0625 0.0390625 The following sub-table either reads each frame four times or allows for 100fps; Circa 100MHz f f(kHz) f(MHz) T periodic T periodic(ns) T periodic(µ) T aer_stream 100 0.1 0.0001 0.01 10000000 10000 T pixel 102400 102.4 0.1024 9.76563E- 06 9765.625 9.765625 T spike 25600000 25600 25.6 3.90625E- 08 39.0625 0.0390625 T partial_spike circa 10ns 102400000 102400 102.4 9.76563E- 09 9.765625 0.009765625 Using a 100MHz clock and showing the effect on T partial_spike ! Exactly 100MHz f f(kHz) f(MHz) T periodic T periodic(ns) T periodic(µ) T aer_stream 97.65625 0.0976563 9.77E-05 0.01024 10240000 10240 T pixel 100000 100 0.1 0.00001 10000 10 T spike 25000000 25000 25 0.00000004 40 0.04 T partial_spike exactly 10ns 100000000 100000 100 0.00000001 10 0.01 Table 12 simulation clocking 95 of 200
5.2 Power Analysis Xilinx FPGAs have a power analyser facility an example screenprint is shown here for power analysis after the implementation of a 16 pixel (colour) receiver chip within FPGA fabric. The quiescent power is 0.60006w, dynamic power is 0.03772w (37.72mw). Figure 47 receiver power analysis 96 of 200
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
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1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
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Adaptive linear combiner w 0 1 Let
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is correct (one class) and -1 (the
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x2 Linear separation 1.00 0.90 0.80
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This is also the Cartesian co-ordin
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2.4 Comparison to Frame Based Repre
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Typical GOP structure (Typically an
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point is an event occurs for spike
Page 45 and 46: 2.5.1 Files in Appendix A “ycut.m
Page 47 and 48: MPEG-2 setup AER setup Camera Camer
Page 49 and 50: 2.6.2 FPGA representation of epi_re
Page 51 and 52: Chapter 3 Concepts An epiretinal im
Page 53 and 54: AER Transmission lines INPUT image
Page 55 and 56: electrical pulse generated is calle
Page 57 and 58: Figure 25 Retinal colour processing
Page 59 and 60: cells to modulate this luminance pa
Page 61 and 62: L+ M- + - R-G G-R B-Y Y-B Note: L(r
Page 63 and 64: 3.6.2 Retinal operations Light reac
Page 65 and 66: quantified by number of cycles pres
Page 67 and 68: (Where * is the convolution operato
Page 69 and 70: T frame C * R * M p Tpacket i.e. Tp
Page 71 and 72: e relaxed and from (2) the temporal
Page 73 and 74: one tw o three four five six seven
Page 75 and 76: 3.8.1 Other test images For other b
Page 77 and 78: Tspike (4ms) Ispike (16ms: interspi
Page 79 and 80: INDIGO ORANGE YELLOW MAGENTA CYAN B
Page 81 and 82: 4.1 Sender concepts From chapter on
Page 83 and 84: pixel must equate to 0.02/1024 i.e.
Page 85 and 86: Clocking hierarchy (32 by 32 image)
Page 87 and 88: the number of address bits will alt
Page 89 and 90: Translation report, (3) Map report,
Page 91 and 92: 90 of 200 CLKIN_IN RST_IN pixelcloc
Page 93 and 94: incorporate colour planes for each
Page 95: Chapter 5 Receiver chip The followi
Page 99 and 100: 98 of 200 produce_wire _outputs Ins
Page 101 and 102: 5.5.1 Incoming (short) AER stream T
Page 103 and 104: Receiver Red plane r1 DAC (4-bit) T
Page 105 and 106: 5.8.2 Electrode size and positionin
Page 107 and 108: sequence of wiring from the receive
Page 109 and 110: does this is to inject an equivalen
Page 111 and 112: 6.2.2 Envisaged retinal array This
Page 113 and 114: a monochrome camera in this space i
Page 115 and 116: 632mW) thus extending battery life
Page 117 and 118: For the implemented/structural case
Page 119 and 120: The sender and receiver circuitry p
Page 121 and 122: Bibliography 1. Woodburn R. Murray
Page 123 and 124: 38. Banks, D.J., P. Degenaar, and C
Page 125 and 126: 74. Freeman, J.A., Skapura, D. M.,
Page 127 and 128: 109. Weiland, J.D., et al. Progress
Page 129 and 130: 141. Indiveri G. Chicca E. Douglas
Page 131 and 132: 172. Singh, P.R., et al. A matched
Page 133 and 134: 206. Stieglitz, T., et al. Developm
Page 135 and 136: xmixedsource; numberOfFrames = 8; f
Page 137 and 138: %check {k} =imread (['D:\abc\subima
Page 139 and 140: %Two for loops the first (outer loo
Page 141 and 142: %Row break rr6c1=000; rr6c2=000; rr
Page 143 and 144: --Appendix B FPGA Test setup librar
Page 145 and 146: stream_blue_pulse_count: out std_lo
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DVI_XCLK_P clock_25MHz, spike_cloc
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use IEEE.STD_LOGIC_UNSIGNED.ALL; --
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--Appendix C FPGA Sender chip libra
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-- else -- resit '1', CLKDV_OUT =>
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FPGA Receiver (structural) chip --A
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FPGA Receiver (structural) chip --E
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FPGA Receiver (structural) chip --r
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FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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