Retinal Prosthesis Dissertation - Student Home Pages

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Chapter 4 Sender chip The purpose of the sender chip is to convert an incoming signal from its conventional representation to an AER format suitable for transmission to the receiver chip. For the purposes of this work the incoming signal will be in the form of the picture data held in a ROM. This picture data initially being in the form of a test image of 32 by 32 i.e. 1024 pixel count, this being later revised to a smaller test image for implementation. Eventually this source will be replaced by a direct camera input as indicated by the following diagram, ideally the camera would output in RGB format to alleviate pre-processing from other formats such as YUV. Test scene (from camera) SENDER - Accept, and process scene into AER protocol AER Transmission lines RECEIVER chip (routes signals to implants) Figure 36; Envisaged System
4.1 Sender concepts From chapter one we know that the maximum address event time for an AER packet representing the pixel of a 1024 pixel count image can be 39062.5ns therefore the full image would take 1024*39062.5 = 40000000ns i.e. 40ms. The figure calculated for spike time (T spike ) on this basis was 156.25ns and for T pulse was 781.25ns i.e. 5* T spike . The AER packet time (T packet ) aka T pixel can be shortened at the expense of increased fps the chart (taken from fps_calcs.xls) demonstrates this relationship. 45000 40000 35000 30000 25000 Tpacket 20000 fps Tae (ns) 15000 10000 5000 0 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79 82 85 88 91 94 97 100 fps Figure 37 T ae versus fps
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
Page 29 and 30: 1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
Page 31 and 32: Adaptive linear combiner w 0 1 Let
Page 33 and 34: is correct (one class) and -1 (the
Page 35 and 36: x2 Linear separation 1.00 0.90 0.80
Page 37 and 38: This is also the Cartesian co-ordin
Page 39 and 40: 2.4 Comparison to Frame Based Repre
Page 41 and 42: Typical GOP structure (Typically an
Page 43 and 44: point is an event occurs for spike
Page 45 and 46: 2.5.1 Files in Appendix A “ycut.m
Page 47 and 48: MPEG-2 setup AER setup Camera Camer
Page 49 and 50: 2.6.2 FPGA representation of epi_re
Page 51 and 52: Chapter 3 Concepts An epiretinal im
Page 53 and 54: AER Transmission lines INPUT image
Page 55 and 56: electrical pulse generated is calle
Page 57 and 58: Figure 25 Retinal colour processing
Page 59 and 60: cells to modulate this luminance pa
Page 61 and 62: L+ M- + - R-G G-R B-Y Y-B Note: L(r
Page 63 and 64: 3.6.2 Retinal operations Light reac
Page 65 and 66: quantified by number of cycles pres
Page 67 and 68: (Where * is the convolution operato
Page 69 and 70: T frame C * R * M p Tpacket i.e. Tp
Page 71 and 72: e relaxed and from (2) the temporal
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Page 75 and 76: 3.8.1 Other test images For other b
Page 77 and 78: Tspike (4ms) Ispike (16ms: interspi
Page 79: INDIGO ORANGE YELLOW MAGENTA CYAN B
Page 83 and 84: pixel must equate to 0.02/1024 i.e.
Page 85 and 86: Clocking hierarchy (32 by 32 image)
Page 87 and 88: the number of address bits will alt
Page 89 and 90: Translation report, (3) Map report,
Page 91 and 92: 90 of 200 CLKIN_IN RST_IN pixelcloc
Page 93 and 94: incorporate colour planes for each
Page 95 and 96: Chapter 5 Receiver chip The followi
Page 97 and 98: 5.2 Power Analysis Xilinx FPGAs hav
Page 99 and 100: 98 of 200 produce_wire _outputs Ins
Page 101 and 102: 5.5.1 Incoming (short) AER stream T
Page 103 and 104: Receiver Red plane r1 DAC (4-bit) T
Page 105 and 106: 5.8.2 Electrode size and positionin
Page 107 and 108: sequence of wiring from the receive
Page 109 and 110: does this is to inject an equivalen
Page 111 and 112: 6.2.2 Envisaged retinal array This
Page 113 and 114: a monochrome camera in this space i
Page 115 and 116: 632mW) thus extending battery life
Page 117 and 118: For the implemented/structural case
Page 119 and 120: The sender and receiver circuitry p
Page 121 and 122: Bibliography 1. Woodburn R. Murray
Page 123 and 124: 38. Banks, D.J., P. Degenaar, and C
Page 125 and 126: 74. Freeman, J.A., Skapura, D. M.,
Page 127 and 128: 109. Weiland, J.D., et al. Progress
Page 129 and 130: 141. Indiveri G. Chicca E. Douglas
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172. Singh, P.R., et al. A matched
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206. Stieglitz, T., et al. Developm
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xmixedsource; numberOfFrames = 8; f
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%check {k} =imread (['D:\abc\subima
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%Two for loops the first (outer loo
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%Row break rr6c1=000; rr6c2=000; rr
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--Appendix B FPGA Test setup librar
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stream_blue_pulse_count: out std_lo
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DVI_XCLK_P clock_25MHz, spike_cloc
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use IEEE.STD_LOGIC_UNSIGNED.ALL; --
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--Appendix C FPGA Sender chip libra
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-- else -- resit '1', CLKDV_OUT =>
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FPGA Receiver (structural) chip --A
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FPGA Receiver (structural) chip --E
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FPGA Receiver (structural) chip --r
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FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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