Retinal Prosthesis Dissertation - Student Home Pages

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5.3 Receiver schematics In figure 47 the first block: “pulse_count_to_AER_stream receives from the sender chip the AER stream formatted as address bits followed by a payload of 18 bits of colour data. The 16 pixel image to be dealt with has 4 address bits associated with the payload. This block converts the payload from a pulse count to a string of 50 bits for each colour plane, retains the pixel address and outputs a 154 bit stream. The second block “preform_for_electrodes” separates the planes of colour into three separate streams with each plane of colour retaining the pixel address with which it is associated, giving the potential for each plane of colour to be addressed separately. The third block (produce_colour_data_streams) strips out the address bits and continues the processing sequentially on each plane of colour data. Block four (fully_extend_data_streams) packs the colour data into pixel length streams to be fed into the routing stage. Block five, the routing stage (produce_wire_outputs) has a twofold function (1) it routes the pixel streams to the relevant inputs to the electrodes driving circuitry (2) it allows routing adjustments to be made where necessary within the software environment. 97 of 200
98 of 200 produce_wire _outputs Inst_produce_ wire_outputs blue(999:0) green(999:0) red(999:0) extended_blue (999:0) extended_red (999:0) extended_green (999:0) blue_data _incoming (49:0) fully_extend_ data_streams Inst_fully_extend_data_ streams green_data _incoming( 49:0) red_data_ incoming( 49:0) pulse_count_to_ AER_stream blue_data _out(49:0) green_data _out(49:0) red_data_ out(49:0) produce_colour _data_streams B_pulse_ count(5:0) R_pulse_ count(5:0) single_address (3::0) pcs_clock G_pulse_ count(5:0) Inst_pulse_count_to _AER_stream XST_GND g gnd Inst_produce_colour _data_streams preform_for_ electrodes Inst_preform_ for_electrodes blue (57:0) green (57:0) red (57:0) blue_with _address (57:0) green_with _address (57:0) red_with_ address (57:0) this_spike_ clock spike_data _clock incoming _stream( 153:0) AER_RGB_pulse _stream(153:0) preform _clock blue_1(3:0) blue_16(3:0) blue_14(3:0) blue_13(3:0) blue_12(3:0) blue_11(3:0) blue_10(3:0) blue_9(3:0) blue_8(3:0) blue_7(3:0) blue_6(3:0) blue_5(3:0) blue_4(3:0) blue_3(3:0) blue_2(3:0) blue_15(3:0) green_16(3:0) green_14(3:0) green_13(3:0) green_12(3:0) green_11(3:0) green_10(3:0) green_9(3:0) green_8(3:0) green_7(3:0) green_6(3:0) green_5(3:0) green_4(3:0) green_3(3:0) green_2(3:0) green_15(3:0) red_16(3:0) red_14(3:0) red_13(3:0) red_12(3:0) red_11(3:0) red_10(3:0) red_9(3:0) red_8(3:0) red_7(3:0) red_6(3:0) red_5(3:0) red_4(3:0) red_3(3:0) red_2(3:0) red_15(3:0) green_1(3:0) red_1(3:0) IO_L15P_15(3:0) IO_L15N_15(3:0) IO_L16P_15(3:0) IO_L16N_15(3:0) IO_L17P_15(3:0) IO_L17N_15(3:0) IO_L18P_15(3:0) IO_L18N_15(3:0) IO_L19P_15(3:0) IO_L19N_15(3:0) IO_L13P_17(3:0) IO_L13N_17(3:0) IO_L14P_17(3:0) IO_L15P_17(3:0) IO_L15N_17(3:0) IO_L16P_17(3:0) IO_L13P_15(3:0) IO_L19N_13(3:0) IO_L19P_13(3:0) IO_L18N_13(3:0) IO_L18P_13(3:0) IO_L17N_13(3:0) IO_L17P_13(3:0) IO_L16N_13(3:0) IO_L16P_13(3:0) IO_L15N_13(3:0) IO_L15P_13(3:0) IO_L14P_13(3:0) IO_L13N_13(3:0) IO_L13P_13(3:0) IO_L13N_15(3:0) IO_L18N_12(3:0) IO_L18P_12(3:0) IO_L17N_12(3:0) IO_L17P_12(3:0) IO_L16N_12(3:0) IO_L16P_12(3:0) IO_L15N_12(3:0) IO_L15P_12(3:0) IO_L14P_12(3:0) IO_L13N_12(3:0) IO_L13P_12(3:0) IO_L14P_11(3:0) IO_L13N_11(3:0) IO_L13P_11(3:0) IO_L14P_15(3:0) IO_L19P_12(3:0) IO_L19N_12(3:0) CLKIN_IN RST_IN pixelclock_dcm CLKDV_OUT LOCKED_OUT CLKO_OUT CLKIN_IBUFG_ OUT P VCC XST_VCC USER_ CLK Inst_pixelclock_dcm get_spike_on_from_partial _spike_clock partial_spike_clock spike_clock biphasic _clock Inst_get_spike_on_from_partial_ spike_clock get_pixel_clock_from_partial_spike _clock partial_spike_clock pixel_clock wire_ clock out_clock get_partial_clock_from _incoming_clock Inst_get_partial_clock_from _incoming_clock received_clock Figure 48 receiver rtl_16
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
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1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
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Adaptive linear combiner w 0 1 Let
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is correct (one class) and -1 (the
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x2 Linear separation 1.00 0.90 0.80
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This is also the Cartesian co-ordin
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2.4 Comparison to Frame Based Repre
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Typical GOP structure (Typically an
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point is an event occurs for spike
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2.5.1 Files in Appendix A “ycut.m
Page 47 and 48: MPEG-2 setup AER setup Camera Camer
Page 49 and 50: 2.6.2 FPGA representation of epi_re
Page 51 and 52: Chapter 3 Concepts An epiretinal im
Page 53 and 54: AER Transmission lines INPUT image
Page 55 and 56: electrical pulse generated is calle
Page 57 and 58: Figure 25 Retinal colour processing
Page 59 and 60: cells to modulate this luminance pa
Page 61 and 62: L+ M- + - R-G G-R B-Y Y-B Note: L(r
Page 63 and 64: 3.6.2 Retinal operations Light reac
Page 65 and 66: quantified by number of cycles pres
Page 67 and 68: (Where * is the convolution operato
Page 69 and 70: T frame C * R * M p Tpacket i.e. Tp
Page 71 and 72: e relaxed and from (2) the temporal
Page 73 and 74: one tw o three four five six seven
Page 75 and 76: 3.8.1 Other test images For other b
Page 77 and 78: Tspike (4ms) Ispike (16ms: interspi
Page 79 and 80: INDIGO ORANGE YELLOW MAGENTA CYAN B
Page 81 and 82: 4.1 Sender concepts From chapter on
Page 83 and 84: pixel must equate to 0.02/1024 i.e.
Page 85 and 86: Clocking hierarchy (32 by 32 image)
Page 87 and 88: the number of address bits will alt
Page 89 and 90: Translation report, (3) Map report,
Page 91 and 92: 90 of 200 CLKIN_IN RST_IN pixelcloc
Page 93 and 94: incorporate colour planes for each
Page 95 and 96: Chapter 5 Receiver chip The followi
Page 97: 5.2 Power Analysis Xilinx FPGAs hav
Page 101 and 102: 5.5.1 Incoming (short) AER stream T
Page 103 and 104: Receiver Red plane r1 DAC (4-bit) T
Page 105 and 106: 5.8.2 Electrode size and positionin
Page 107 and 108: sequence of wiring from the receive
Page 109 and 110: does this is to inject an equivalen
Page 111 and 112: 6.2.2 Envisaged retinal array This
Page 113 and 114: a monochrome camera in this space i
Page 115 and 116: 632mW) thus extending battery life
Page 117 and 118: For the implemented/structural case
Page 119 and 120: The sender and receiver circuitry p
Page 121 and 122: Bibliography 1. Woodburn R. Murray
Page 123 and 124: 38. Banks, D.J., P. Degenaar, and C
Page 125 and 126: 74. Freeman, J.A., Skapura, D. M.,
Page 127 and 128: 109. Weiland, J.D., et al. Progress
Page 129 and 130: 141. Indiveri G. Chicca E. Douglas
Page 131 and 132: 172. Singh, P.R., et al. A matched
Page 133 and 134: 206. Stieglitz, T., et al. Developm
Page 135 and 136: xmixedsource; numberOfFrames = 8; f
Page 137 and 138: %check {k} =imread (['D:\abc\subima
Page 139 and 140: %Two for loops the first (outer loo
Page 141 and 142: %Row break rr6c1=000; rr6c2=000; rr
Page 143 and 144: --Appendix B FPGA Test setup librar
Page 145 and 146: stream_blue_pulse_count: out std_lo
Page 147 and 148: DVI_XCLK_P clock_25MHz, spike_cloc
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use IEEE.STD_LOGIC_UNSIGNED.ALL; --
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--Appendix C FPGA Sender chip libra
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-- else -- resit '1', CLKDV_OUT =>
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FPGA Receiver (structural) chip --A
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FPGA Receiver (structural) chip --E
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FPGA Receiver (structural) chip --r
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FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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