Retinal Prosthesis Dissertation - Student Home Pages

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OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails. IO Utilization: Number of bonded IOBs: 23 out of 480 4% IOB Flip Flops: 4 Place and route report example Release 11.4 par L.68 (nt) Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. EECEAYPG11: Thu May 20 14:36:09 2010 par -ise imp_send_1024.ise -w -intstyle ise -ol std -t 1 top_wrapper_map.ncd top_wrapper.ncd top_wrapper.pcf Constraints file: top_wrapper.pcf. "top_wrapper" is an NCD, version 3.2, device xc5vlx50t, package ff1136, speed -3 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv vv INFO: Security: 54 - 'xc5vlx50t' is a WebPack part. ---------------------------------------------------------------------- INFO: Par: 465 - The PAR option, "-t" (Starting Placer Cost Table), will be disabled in the next software release when used in combination with MAP -timing (Perform Timing-Driven Packing and Placement) or when run with V5 or newer architectures. To explore cost tables, please use the MAP option, "-t" (Starting Placer Cost Table), instead. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) INFO: Par: 282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". Device speed data version: "PRODUCTION 1.66 2009-11-16". Device Utilization Summary: Number of BUFGs 4 out of 32 12% Number of DCM_ADVs 1 out of 12 8% Number of External IOBs 29 out of 480 6% Number of LOCed IOBs 0 out of 29 0% Number of OLOGICs 10 out of 560 1% Number of RAMB36_EXPs 1 out of 60 1% Number of Slice Registers 145 out of 28800 1% Number used as Flip Flops 142 Number used as Latches 3 Number used as LatchThrus 0 Number of Slice LUTS 208 out of 28800 1% Number of Slice LUT-Flip Flop pairs 217 out of 28800 1% Overall effort level (-ol): Standard 177 of 200
Router effort level (-rl): Standard Starting initial Timing Analysis. REAL time: 17 secs Finished initial Timing Analysis. REAL time: 17 secs Starting Router Wirelength Stats for nets on all pins. NumPins: 812 Phase 1: 1080 unrouted; REAL time: 18 secs Phase 2: 763 unrouted; REAL time: 19 secs Phase 3: 172 unrouted; REAL time: 19 secs Phase 4: 172 unrouted; (Par is working to improve performance) REAL time: 25 secs Phase 5: 0 unrouted; (Par is working to improve performance) REAL time: 26 secs Phase 6: 0 unrouted; (Par is working to improve performance) REAL time: 26 secs Phase 7: 0 unrouted; (Par is working to improve performance) REAL time: 26 secs Phase 8: 0 unrouted; (Par is working to improve performance) REAL time: 26 secs Phase 9: 0 unrouted; (Par is working to improve performance) REAL time: 27 secs Phase 10: 0 unrouted; (Par is working to improve performance) REAL time: 27 secs Total REAL time to Router completion: 27 secs Total CPU time to Router completion: 26 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew (ns) |Max Delay (ns)| +---------------------+--------------+------+------+------------+-------------+ |Inst_get_spike_on_fr | | | | | | |om_partial_spike_clo | | | | | | | ck/clk_sig |BUFGCTRL_X0Y30| No | 24 | 0.077 | 1.479 | +---------------------+--------------+------+------+------------+-------------+ |Inst_get_partial_spi | | | | | | |ke_clock_from_incomi | | | | | | |ng_clock/slow_clk_si | | | | | | | g |BUFGCTRL_X0Y31| No | 16 | 0.034 | 1.367 | +---------------------+--------------+------+------+------------+-------------+ | incoming_clock | BUFGCTRL_X0Y0| No | 8 | 0.028 | 1.355 | +---------------------+--------------+------+------+------------+-------------+ |Inst_get_pixel_clock | | | | | | |_from_partial_spike_ | | | | | | | clock/slow_clk_sig | Local| | 6 | 0.411 | 0.789 | +---------------------+--------------+------+------+------------+-------------+ |Inst_get_pixel_clock | | | | | | 178 of 200
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
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1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
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Adaptive linear combiner w 0 1 Let
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is correct (one class) and -1 (the
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x2 Linear separation 1.00 0.90 0.80
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This is also the Cartesian co-ordin
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2.4 Comparison to Frame Based Repre
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Typical GOP structure (Typically an
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point is an event occurs for spike
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2.5.1 Files in Appendix A “ycut.m
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MPEG-2 setup AER setup Camera Camer
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2.6.2 FPGA representation of epi_re
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Chapter 3 Concepts An epiretinal im
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AER Transmission lines INPUT image
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electrical pulse generated is calle
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Figure 25 Retinal colour processing
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cells to modulate this luminance pa
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L+ M- + - R-G G-R B-Y Y-B Note: L(r
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3.6.2 Retinal operations Light reac
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quantified by number of cycles pres
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(Where * is the convolution operato
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T frame C * R * M p Tpacket i.e. Tp
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e relaxed and from (2) the temporal
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one tw o three four five six seven
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3.8.1 Other test images For other b
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Tspike (4ms) Ispike (16ms: interspi
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INDIGO ORANGE YELLOW MAGENTA CYAN B
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4.1 Sender concepts From chapter on
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pixel must equate to 0.02/1024 i.e.
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Clocking hierarchy (32 by 32 image)
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the number of address bits will alt
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Translation report, (3) Map report,
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90 of 200 CLKIN_IN RST_IN pixelcloc
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incorporate colour planes for each
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Chapter 5 Receiver chip The followi
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5.2 Power Analysis Xilinx FPGAs hav
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98 of 200 produce_wire _outputs Ins
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5.5.1 Incoming (short) AER stream T
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Receiver Red plane r1 DAC (4-bit) T
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5.8.2 Electrode size and positionin
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sequence of wiring from the receive
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does this is to inject an equivalen
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6.2.2 Envisaged retinal array This
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a monochrome camera in this space i
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632mW) thus extending battery life
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For the implemented/structural case
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The sender and receiver circuitry p
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Bibliography 1. Woodburn R. Murray
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38. Banks, D.J., P. Degenaar, and C
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74. Freeman, J.A., Skapura, D. M.,
Page 127 and 128: 109. Weiland, J.D., et al. Progress
Page 129 and 130: 141. Indiveri G. Chicca E. Douglas
Page 131 and 132: 172. Singh, P.R., et al. A matched
Page 133 and 134: 206. Stieglitz, T., et al. Developm
Page 135 and 136: xmixedsource; numberOfFrames = 8; f
Page 137 and 138: %check {k} =imread (['D:\abc\subima
Page 139 and 140: %Two for loops the first (outer loo
Page 141 and 142: %Row break rr6c1=000; rr6c2=000; rr
Page 143 and 144: --Appendix B FPGA Test setup librar
Page 145 and 146: stream_blue_pulse_count: out std_lo
Page 147 and 148: DVI_XCLK_P clock_25MHz, spike_cloc
Page 149 and 150: use IEEE.STD_LOGIC_UNSIGNED.ALL; --
Page 151 and 152: --Appendix C FPGA Sender chip libra
Page 153 and 154: -- else -- resit '1', CLKDV_OUT =>
Page 155 and 156: FPGA Receiver (structural) chip --A
Page 157 and 158: FPGA Receiver (structural) chip --E
Page 159 and 160: FPGA Receiver (structural) chip --r
Page 161 and 162: FPGA Receiver (structural) chip blu
Page 163 and 164: FPGA Receiver (structural) chip con
Page 165 and 166: FPGA Receiver (structural) chip --s
Page 167 and 168: FPGA Receiver (structural) chip --
Page 169 and 170: FPGA Receiver (structural) chip --
Page 171 and 172: FPGA Receiver (structural) chip IO_
Page 173 and 174: Number with an unused LUT 18 219 8%
Page 175 and 176: IO Utilization: Number of IOs: 26 N
Page 177: The Slice Logic Distribution report
Page 181 and 182: oming_clock | HOLD | 0.519ns| | 0|
Page 183 and 184: Part | xc5vlx50tff1136-3 | Process
Page 185 and 186: Selected Device: 5vlx50tff1136-3 Sl
Page 187 and 188: used in combination with MAP -timin
Page 189 and 190: Data Sheet report: ----------------
Page 191 and 192: “For these implantable devices to
Page 193 and 194: microstimulator with a 1:4 demultip
Page 195 and 196: “Medical experiments have estimat
Page 197 and 198: A Retinomorphic Vision System “In
Page 199 and 200: “The common language of neuromorp
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