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FPGA Receiver (structural) chip
0);
downto 0);
0)
);
END COMPONENT;
red_outgoing_address: IN std_logic_vector (5 downto
green_outgoing_address: IN std_logic_vector (5
blue_outgoing_address: IN std_logic_vector (5 downto
COMPONENT get_rc_addresses_with_data is --Starting at the ZERO'TH
single_address.
Port (address_with_data: in STD_LOGIC_VECTOR (61 downto 0) ;
row_address: out STD_LOGIC_VECTOR (5 downto 0);
column_address: out STD_LOGIC_VECTOR (5 downto 0)
); --Fed from "AER_sep_streams_with_incoming_addresses"
END COMPONENT;
COMPONENT file_support_wire_outputs is
Port (an_pixel_clock: in STD_LOGIC;--pixel_clock
in_red_wire_1: in STD_LOGIC_VECTOR (49 downto 0);
in_red_wire_2: in STD_LOGIC_VECTOR (49 downto 0);
in_red_wire_3: in STD_LOGIC_VECTOR (49 downto 0);
in_red_wire_4: in STD_LOGIC_VECTOR (49 downto 0);
in_green_wire_1: in STD_LOGIC_VECTOR (49 downto 0);
in_green_wire_2: in STD_LOGIC_VECTOR (49 downto 0);
in_green_wire_3: in STD_LOGIC_VECTOR (49 downto 0);
in_green_wire_4: in STD_LOGIC_VECTOR (49 downto 0);
in_blue_wire_1: in STD_LOGIC_VECTOR (49 downto 0);
in_blue_wire_2: in STD_LOGIC_VECTOR (49 downto 0);
in_blue_wire_3: in STD_LOGIC_VECTOR (49 downto 0);
in_blue_wire_4: in STD_LOGIC_VECTOR (49 downto 0)
);
END COMPONENT; --end file_support_wire_outputs;
COMPONENT pulse_count_to_AER_stream is
Port (
pcs_clk: in STD_LOGIC;
single_address: in STD_LOGIC_VECTOR (3 downto
0); --short_AER_RGB_stream (19 downto 18)
R_pulse_count: in STD_LOGIC_VECTOR (5 downto
0); --short_AER_RGB_stream (17 downto 12)
G_pulse_count: in STD_LOGIC_VECTOR (5 downto
0);--short_AER_RGB_stream (11 downto 6)
B_pulse_count: in STD_LOGIC_VECTOR (5 downto
0); --short_AER_RGB_stream (5 downto 0)
AER_RGB_pulse_stream: out STD_LOGIC_VECTOR
(153 downto 0)
);
END COMPONENT;
subtype limited_current is integer range -70 to +70;
--signal num: limited_current;
--pixel time equals 39062.5 ns (@25fps), note that 25MHz has the periodic time of
40ns approx.
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