Retinal Prosthesis Dissertation - Student Home Pages

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4.2 Sender AER format Each AER packet; representing a pixel, contains address bits followed by a pulse count for each plane of colour within the pixel. An example of the first row of a 32 by 32 image is shown in the following table of values. The first ten bits are the address bits and the remaining 18 bits represent the data containing colour information in the form of a pulse count. 0000000001 110010000000000000 0000000010 110010000000000000 0000000011 110010000000000000 0000000100 110010000000000000 0000000101 000000110010000000 0000000110 000000110010000000 0000000111 000000110010000000 0000001000 000000110010000000 0000001001 000000000000110010 0000001010 000000000000110010 0000001011 000000000000110010 0000001100 000000000000110010 0000001101 000000110010110010 0000001110 000000110010110010 0000001111 000000110010110010 0000010000 000000110010110010 0000010001 110010000000110010 0000010010 110010000000110010 0000010011 110010000000110010 0000010100 110010000000110010 0000010101 110010110010000000 0000010110 110010110010000000 0000010111 110010110010000000 0000011000 110010110010000000 0000011001 110010011001000000 0000011010 110010011001000000 0000011011 110010011001000000 0000011100 110010011001000000 0000011101 011001000000011001 0000011110 011001000000011001 0000011111 011001000000011001 0000100000 011001000000011001 red green blue cyan magenta yellow orange Indigo Table 8 short AER format In the example shown there are ten address bits and eighteen bits for the AER `payload’ this payload will always be eighteen bits regardless of image size whereas 85 of 200
the number of address bits will alter with image size. The number of address bits required for various image sizes can be calculated from the following formula; where the answer obtained is rounded up to the nearest whole number. Log (pixel_count)/log2 side of square address bits log image 10 pixel_count required Total bit length 2 0.60206 4 2 20 4 1.20412 16 4 22 8 1.80618 64 6 24 16 2.40824 256 8 26 32 3.0103 1024 10 28 1024 6.0206 1048576 20 38 Table 9 example correspondences 4.2.1 Alternative (discounted) sender AER format An alternative robust AER format can be constructed whereby the bitstream consists of ten bits of address (32 by 32 image) followed by a payload of 150 bits of which the first 50 bits encode red plane information; the second 50 bits encode green plane information and finally 50 bits of blue plane information. Such a format would be more error tolerant in terms of loss of bits within the payload e.g. a two bit error would be negligible but could only be achieved if a longer bit stream could be tolerated. As this format will be integral to the receiver chip design it can justifiably be used as part of the test setup to demonstrate that such a format can be output to a monitor to display the picture expected to be formed. Programming components (or extracts thereof) will be included in appendix B of this thesis. 86 of 200
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
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1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
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Adaptive linear combiner w 0 1 Let
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is correct (one class) and -1 (the
Page 35 and 36: x2 Linear separation 1.00 0.90 0.80
Page 37 and 38: This is also the Cartesian co-ordin
Page 39 and 40: 2.4 Comparison to Frame Based Repre
Page 41 and 42: Typical GOP structure (Typically an
Page 43 and 44: point is an event occurs for spike
Page 45 and 46: 2.5.1 Files in Appendix A “ycut.m
Page 47 and 48: MPEG-2 setup AER setup Camera Camer
Page 49 and 50: 2.6.2 FPGA representation of epi_re
Page 51 and 52: Chapter 3 Concepts An epiretinal im
Page 53 and 54: AER Transmission lines INPUT image
Page 55 and 56: electrical pulse generated is calle
Page 57 and 58: Figure 25 Retinal colour processing
Page 59 and 60: cells to modulate this luminance pa
Page 61 and 62: L+ M- + - R-G G-R B-Y Y-B Note: L(r
Page 63 and 64: 3.6.2 Retinal operations Light reac
Page 65 and 66: quantified by number of cycles pres
Page 67 and 68: (Where * is the convolution operato
Page 69 and 70: T frame C * R * M p Tpacket i.e. Tp
Page 71 and 72: e relaxed and from (2) the temporal
Page 73 and 74: one tw o three four five six seven
Page 75 and 76: 3.8.1 Other test images For other b
Page 77 and 78: Tspike (4ms) Ispike (16ms: interspi
Page 79 and 80: INDIGO ORANGE YELLOW MAGENTA CYAN B
Page 81 and 82: 4.1 Sender concepts From chapter on
Page 83 and 84: pixel must equate to 0.02/1024 i.e.
Page 85: Clocking hierarchy (32 by 32 image)
Page 89 and 90: Translation report, (3) Map report,
Page 91 and 92: 90 of 200 CLKIN_IN RST_IN pixelcloc
Page 93 and 94: incorporate colour planes for each
Page 95 and 96: Chapter 5 Receiver chip The followi
Page 97 and 98: 5.2 Power Analysis Xilinx FPGAs hav
Page 99 and 100: 98 of 200 produce_wire _outputs Ins
Page 101 and 102: 5.5.1 Incoming (short) AER stream T
Page 103 and 104: Receiver Red plane r1 DAC (4-bit) T
Page 105 and 106: 5.8.2 Electrode size and positionin
Page 107 and 108: sequence of wiring from the receive
Page 109 and 110: does this is to inject an equivalen
Page 111 and 112: 6.2.2 Envisaged retinal array This
Page 113 and 114: a monochrome camera in this space i
Page 115 and 116: 632mW) thus extending battery life
Page 117 and 118: For the implemented/structural case
Page 119 and 120: The sender and receiver circuitry p
Page 121 and 122: Bibliography 1. Woodburn R. Murray
Page 123 and 124: 38. Banks, D.J., P. Degenaar, and C
Page 125 and 126: 74. Freeman, J.A., Skapura, D. M.,
Page 127 and 128: 109. Weiland, J.D., et al. Progress
Page 129 and 130: 141. Indiveri G. Chicca E. Douglas
Page 131 and 132: 172. Singh, P.R., et al. A matched
Page 133 and 134: 206. Stieglitz, T., et al. Developm
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%check {k} =imread (['D:\abc\subima
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%Two for loops the first (outer loo
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%Row break rr6c1=000; rr6c2=000; rr
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--Appendix B FPGA Test setup librar
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stream_blue_pulse_count: out std_lo
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DVI_XCLK_P clock_25MHz, spike_cloc
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use IEEE.STD_LOGIC_UNSIGNED.ALL; --
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--Appendix C FPGA Sender chip libra
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-- else -- resit '1', CLKDV_OUT =>
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FPGA Receiver (structural) chip --A
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FPGA Receiver (structural) chip --E
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FPGA Receiver (structural) chip --r
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FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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