Retinal Prosthesis Dissertation - Student Home Pages

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3.6 Current Retinal Implants Commonality exists between sub retinal [195, 196] and epi-retinal approaches in terms of stimulus pulse requirements to be delivered by the implants. The difference between these two approaches is that the sub retinal implant is meant to substitute for retinal processing within the outer retina whereas the epi-retinal implant bypasses both the inner and outer retina and uses signals derived from a camera to produce the stimulus pulsing. 3.6.1 Retinal structure There are five major classes of neuron within the retina which can be considered to lie within the seven layers of the following representation (Figure 1) of a cross section of the retinal architecture; namely cones and rods, horizontal, amacrine and retinal ganglion cells (RGCs). The outer retina extends from the pigment epithelium to the boundary of the inner nuclear layer whilst the inner retina encompasses the inner nuclear layer, the inner plexiform layer and the ganglion cell layer. The synaptic layers housing ion channels are the outer plexiform layer (OPL) and the inner plexiform layer (IPL). A sub retinal implant (section 1.1.1) [197] would occupy the space of photoreceptors in a healthy retina i.e. adjacent to the choroid (the retinal pigment epithelium (RPE) lines the choroid), the photodiodes taking the place of photoreceptors and the stimulatory electrodes impinging at the boundary of the inner nuclear layer and typically but not exclusively stimulating bipolar cells. An epi retinal implant (section 1.1.2) [111] is tacked to the inner limiting membrane of the retina at the axon side of the ganglion layer reached from the inside of the eyeball. 61 of 200
3.6.2 Retinal operations Light reaching the photoreceptors (section 3.4) of which there are 126 x 10 6 over the whole human retina (section 3.4), is transduced into electrical signals synapsing onto bipolar and horizontal cells. The cones represent a twentieth of the photoreceptors however their dendritic arbor is typically larger than that of the rods. Bearing in mind that the optic nerve has only 1.2 million fibres [174] then it can be seen that the retina is operating as a very efficient spatiotemporal filter. Photoreceptors threshold and summate; with horizontal cells providing lateral processing, by interacting with photoreceptor and bipolar cells. Amacrine cells also provide lateral processing in the inner retina by interacting with bipolar cells and RGCs. 62 of 200
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
Page 11 and 12: Chapter 1 Introduction/research aim
Page 13 and 14: foveola (fovea pit) there is a one
Page 15 and 16: NB that the photoreceptors of the f
Page 17 and 18: electrodes to be driven implies sti
Page 19 and 20: Typically AER is used as a multi se
Page 21 and 22: Real time - innerpulse relationship
Page 23 and 24: the post processing stage of this w
Page 25 and 26: Appendix C: FPGA Sender chip Append
Page 27 and 28: Red (660nm) R / G Red ( 620750nm )
Page 29 and 30: 1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
Page 31 and 32: Adaptive linear combiner w 0 1 Let
Page 33 and 34: is correct (one class) and -1 (the
Page 35 and 36: x2 Linear separation 1.00 0.90 0.80
Page 37 and 38: This is also the Cartesian co-ordin
Page 39 and 40: 2.4 Comparison to Frame Based Repre
Page 41 and 42: Typical GOP structure (Typically an
Page 43 and 44: point is an event occurs for spike
Page 45 and 46: 2.5.1 Files in Appendix A “ycut.m
Page 47 and 48: MPEG-2 setup AER setup Camera Camer
Page 49 and 50: 2.6.2 FPGA representation of epi_re
Page 51 and 52: Chapter 3 Concepts An epiretinal im
Page 53 and 54: AER Transmission lines INPUT image
Page 55 and 56: electrical pulse generated is calle
Page 57 and 58: Figure 25 Retinal colour processing
Page 59 and 60: cells to modulate this luminance pa
Page 61: L+ M- + - R-G G-R B-Y Y-B Note: L(r
Page 65 and 66: quantified by number of cycles pres
Page 67 and 68: (Where * is the convolution operato
Page 69 and 70: T frame C * R * M p Tpacket i.e. Tp
Page 71 and 72: e relaxed and from (2) the temporal
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Page 75 and 76: 3.8.1 Other test images For other b
Page 77 and 78: Tspike (4ms) Ispike (16ms: interspi
Page 79 and 80: INDIGO ORANGE YELLOW MAGENTA CYAN B
Page 81 and 82: 4.1 Sender concepts From chapter on
Page 83 and 84: pixel must equate to 0.02/1024 i.e.
Page 85 and 86: Clocking hierarchy (32 by 32 image)
Page 87 and 88: the number of address bits will alt
Page 89 and 90: Translation report, (3) Map report,
Page 91 and 92: 90 of 200 CLKIN_IN RST_IN pixelcloc
Page 93 and 94: incorporate colour planes for each
Page 95 and 96: Chapter 5 Receiver chip The followi
Page 97 and 98: 5.2 Power Analysis Xilinx FPGAs hav
Page 99 and 100: 98 of 200 produce_wire _outputs Ins
Page 101 and 102: 5.5.1 Incoming (short) AER stream T
Page 103 and 104: Receiver Red plane r1 DAC (4-bit) T
Page 105 and 106: 5.8.2 Electrode size and positionin
Page 107 and 108: sequence of wiring from the receive
Page 109 and 110: does this is to inject an equivalen
Page 111 and 112: 6.2.2 Envisaged retinal array This
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a monochrome camera in this space i
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632mW) thus extending battery life
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For the implemented/structural case
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The sender and receiver circuitry p
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Bibliography 1. Woodburn R. Murray
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38. Banks, D.J., P. Degenaar, and C
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74. Freeman, J.A., Skapura, D. M.,
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109. Weiland, J.D., et al. Progress
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141. Indiveri G. Chicca E. Douglas
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172. Singh, P.R., et al. A matched
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206. Stieglitz, T., et al. Developm
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xmixedsource; numberOfFrames = 8; f
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%check {k} =imread (['D:\abc\subima
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%Two for loops the first (outer loo
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%Row break rr6c1=000; rr6c2=000; rr
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--Appendix B FPGA Test setup librar
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stream_blue_pulse_count: out std_lo
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DVI_XCLK_P clock_25MHz, spike_cloc
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use IEEE.STD_LOGIC_UNSIGNED.ALL; --
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--Appendix C FPGA Sender chip libra
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-- else -- resit '1', CLKDV_OUT =>
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FPGA Receiver (structural) chip --A
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FPGA Receiver (structural) chip --E
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FPGA Receiver (structural) chip --r
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FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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