Retinal Prosthesis Dissertation - Student Home Pages

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each side would be 1.15 ÷ 0.05 equals 23 giving potentially 23 by 23 equals 529 electrodes (in practice; due to pragmatic limitations 170 i.e (2 x 85)). However three factors need to be born in mind; firstly, 256 wires through a 5mm incision is the present (2012) limitation to electrode connections, secondly for structural implementation of a four by four picture a third of this wiring capability (≈ 85) needs to be available outside of this foveal specific area of the optic disc for the `blue’ signals to the small bistratified RGC’s [213, 214]. Recall the majority of cones fed from the fovea are `red’ and `green’ whereas the `blue’ cone signals directed to the parafoveal retina can use 30µm diameter electrodes to generate larger stimulation sites to resonate [215] with the small bistratified RGC’s; responsible for handling blue cone signals, outside of this foveal specific area of the optic disc. In configuration each plane of the test image can be configured separately to ensure correct placement of the phosphenes. Figure 55 shows the perimeter of 30µm electrodes associated with blue cone signals. The expanded view of the internal portion of the array, with 2µm electrodes; focused over the foveal pit, targets the RGC’s carrying red and green cone signals. Effectively a one-to-one correspondence between stimulation site and electrode 6.2.3 Connecting the detailed engineering to the overall concept Chapter four describes the design and implementation of the sender chip which translates the camera image to an AER format for transmission to the receiver chip described in chapter five. Chapter five describes the routing of the timed signals to the driver circuitry housed atop the retinal implant. Future work could avoid telemetry once a colour camera becomes available that can be housed in the eyeball; 111 of 200
a monochrome camera in this space is already possible, this would resolve issues of variable inductive coupling which presently exist with current retinal implants. 6.2.4 Differences between proposed technique and current retinal implants Current retinal prostheses are asynchronous and achromatic requiring an arbiter in the first case and amplitude variation to attain brightness variation of the greyscale image; in the second case. Any amplitude variation in this approach would be purely for reasons of electrode positioning and patient sensitivity. Current retinal prostheses use comparatively large electrodes relying on pulse duration to resonate correctly with RGC’s, this approach for the inner portion of the retinal implant is synchronous whilst maintaining a frame rate for possible hybrid prostheses, although in principle being pixel based rather than frame based this is not necessary. 112 of 200
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An Address Event Representation (AE
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Abstract\Foreword This document pro
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Contents An Address Event Represent
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--Appendix E FPGA Outputs .........
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Figure 48 receiver rtl_16 .........
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Chapter 1 Introduction/research aim
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foveola (fovea pit) there is a one
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NB that the photoreceptors of the f
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electrodes to be driven implies sti
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Typically AER is used as a multi se
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Real time - innerpulse relationship
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the post processing stage of this w
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Appendix C: FPGA Sender chip Append
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Red (660nm) R / G Red ( 620750nm )
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1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
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Adaptive linear combiner w 0 1 Let
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is correct (one class) and -1 (the
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x2 Linear separation 1.00 0.90 0.80
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This is also the Cartesian co-ordin
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2.4 Comparison to Frame Based Repre
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Typical GOP structure (Typically an
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point is an event occurs for spike
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2.5.1 Files in Appendix A “ycut.m
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MPEG-2 setup AER setup Camera Camer
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2.6.2 FPGA representation of epi_re
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Chapter 3 Concepts An epiretinal im
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AER Transmission lines INPUT image
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electrical pulse generated is calle
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Figure 25 Retinal colour processing
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cells to modulate this luminance pa
Page 61 and 62: L+ M- + - R-G G-R B-Y Y-B Note: L(r
Page 63 and 64: 3.6.2 Retinal operations Light reac
Page 65 and 66: quantified by number of cycles pres
Page 67 and 68: (Where * is the convolution operato
Page 69 and 70: T frame C * R * M p Tpacket i.e. Tp
Page 71 and 72: e relaxed and from (2) the temporal
Page 73 and 74: one tw o three four five six seven
Page 75 and 76: 3.8.1 Other test images For other b
Page 77 and 78: Tspike (4ms) Ispike (16ms: interspi
Page 79 and 80: INDIGO ORANGE YELLOW MAGENTA CYAN B
Page 81 and 82: 4.1 Sender concepts From chapter on
Page 83 and 84: pixel must equate to 0.02/1024 i.e.
Page 85 and 86: Clocking hierarchy (32 by 32 image)
Page 87 and 88: the number of address bits will alt
Page 89 and 90: Translation report, (3) Map report,
Page 91 and 92: 90 of 200 CLKIN_IN RST_IN pixelcloc
Page 93 and 94: incorporate colour planes for each
Page 95 and 96: Chapter 5 Receiver chip The followi
Page 97 and 98: 5.2 Power Analysis Xilinx FPGAs hav
Page 99 and 100: 98 of 200 produce_wire _outputs Ins
Page 101 and 102: 5.5.1 Incoming (short) AER stream T
Page 103 and 104: Receiver Red plane r1 DAC (4-bit) T
Page 105 and 106: 5.8.2 Electrode size and positionin
Page 107 and 108: sequence of wiring from the receive
Page 109 and 110: does this is to inject an equivalen
Page 111: 6.2.2 Envisaged retinal array This
Page 115 and 116: 632mW) thus extending battery life
Page 117 and 118: For the implemented/structural case
Page 119 and 120: The sender and receiver circuitry p
Page 121 and 122: Bibliography 1. Woodburn R. Murray
Page 123 and 124: 38. Banks, D.J., P. Degenaar, and C
Page 125 and 126: 74. Freeman, J.A., Skapura, D. M.,
Page 127 and 128: 109. Weiland, J.D., et al. Progress
Page 129 and 130: 141. Indiveri G. Chicca E. Douglas
Page 131 and 132: 172. Singh, P.R., et al. A matched
Page 133 and 134: 206. Stieglitz, T., et al. Developm
Page 135 and 136: xmixedsource; numberOfFrames = 8; f
Page 137 and 138: %check {k} =imread (['D:\abc\subima
Page 139 and 140: %Two for loops the first (outer loo
Page 141 and 142: %Row break rr6c1=000; rr6c2=000; rr
Page 143 and 144: --Appendix B FPGA Test setup librar
Page 145 and 146: stream_blue_pulse_count: out std_lo
Page 147 and 148: DVI_XCLK_P clock_25MHz, spike_cloc
Page 149 and 150: use IEEE.STD_LOGIC_UNSIGNED.ALL; --
Page 151 and 152: --Appendix C FPGA Sender chip libra
Page 153 and 154: -- else -- resit '1', CLKDV_OUT =>
Page 155 and 156: FPGA Receiver (structural) chip --A
Page 157 and 158: FPGA Receiver (structural) chip --E
Page 159 and 160: FPGA Receiver (structural) chip --r
Page 161 and 162: FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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