Retinal Prosthesis Dissertation - Student Home Pages

In the Xilinx Virtex 5 the DCM has the following possible divisions from either
400MHz or 100MHz: 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12,
13, 14, 1`5 and 16. So one possible combination to obtain 400kHz as the `out_clock’
value would derive 40MHz as the output from the DCM and divide this by 100 in
the programming block labeled “get_partial_clock_from_incoming_clock”. At 5fps
for the same image to obtain 80kHz as the out_clock derive 20MHz as the output
from the DCM and divide this by 250.
In the block “get_spike_on_from_partial_spike_clock” divide by four to get the
spike_clock frequency for all fps e.g. @25fps this would be100kHz.
In the block get pixel_clock_from_partial_spike_clock divide by one thousand to get
the pixel frequency for all fps e.g. @25fps this would be 400Hz
The three instance of the “pulsar” block convert conventional 24 bit colour measure
to a pulse count (described earlier), over time, for each of the three colour planes:
red, green and blue.
The counter counts and outputs the address bits for each pixel as it occurs.
Finally “pulse_count_to_pc_stream” time multiplexes and outputs the AER stream
consisting of AER packets with a payload of 18 bits. The first six bits of the payload
represent the colour intensity for the red plane, followed by six bits for green and
blue planes respectively.
4.6 Chapter summary
The size of the image in pixel count (to be transmitted) will be limited by the number
of electrodes possible at the retinal implant and presently (2010) this is expected to
rise to over 1000 within several years. For the sender chip; programmes were
completed both behaviourally and structurally i.e. synthesised and implemented for
image sizes ranging from 16 pixels (4 by 4) up to 1024 pixels (32 by 32). To
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