Retinal Prosthesis Dissertation - Student Home Pages

--Appendix E FPGA Outputs
`Sender’ design summary
“Design Summary” facility; a recent (December 2010) screenprint is shown here:
imp_send_16 Project Status (12/31/2010 - 14:29:37)
Project
File:
Module
Name:
imp_send_16.ise
Implementation State:
Programming
Generated
top_wrapper Errors: No Errors
File
Target
Device:
xc5vlx50t-3ff1136 Warnings: 27 Warnings
Product
Version:
ISE 11.4
Routing
Results:
All Signals
Completely Routed
Design
Goal:
Balanced
Timing
Constraints:
All Constraints Met
Design
Strategy:
Xilinx
(unlocked)
Default
Final Timing
Score:
0 (Setup: 0, Hold:
0) (Timing Report)
Device Utilization Summary [-]
Slice Logic Utilization
Used Available Utilization Note(s)
Number of Slice Registers 139 28,800 1%
Number used as Flip Flops 136
Number used as Latches 3
Number of Slice LUTs 201 28,800 1%
Number used as logic 198 28,800 1%
Number using O6 output only 105
Number using O5 output only 90
Number using O5 and O6 3
Number used as exclusive routethru
Number of route-thrus 93
Number using O6 output only 93
Number of occupied Slices 67 7,200 1%
Number of LUT Flip Flop pairs used 219
Number with an unused Flip Flop 80 219 36%
3
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