Retinal Prosthesis Dissertation - Student Home Pages

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light falling on an array of photocells the epiretinal approach relies on electrical stimulation data being provided from an external camera. The most well-known artificial retinal/retinal prosthetic is that developed by the “Artificial Retina Project” [53] described in the following way: “A pair of glasses with a small video camera is worn by the patient. The video captured by the camera is sent wirelessly to a belt pack containing a microprocessor that processes the video signal. This processed video signal is sent to an antenna in the eye. The antenna is connected to an array of electrodes that have been implanted directly inside the eye on top of the old retina. The array of electrodes transmits signals that directly stimulate optic nerve cells that are responsible for sending images to the brain’s vision centers. “The `sender’ chip of the system developed here will be that part of the system that processes the camera video signal. Address Event Representation (AER) will be the processed video signal which is then sent to the `receiver’ chip housed in close proximity to the implanted retinal array. The receiver chip will, after post processing of the stimulation data, deliver biphasic current pulses to stimulate the retinal ganglion cells (RGC) via the electrodes of the retinal implant. Due to image size, and hence event activity, increasing the computational load quadratically then behaviorally only a 32 by 32 (1024 pixel) image will be demonstrated. Also due to the FPGA resource being used this prototype implementation will be restricted to a 4 by 4 (16 pixel) image implying 48 electrodes to be driven although with a different resource an 8 by 8 (64 pixel) image implying 192 electrodes to be driven could easily be accommodated within the present 256 wire limit. Should this limit reach circa 1000 then a 16 by 16 (256 pixel image) implying 768 electrodes could also easily be accommodated. An implementation of 32 by 32 (1024 pixels) suggesting 3072 15 of 200
electrodes to be driven implies stimulating 3072 RGC which would still be in the foveal pit which is the area receptive to cones and hence colour stimulation. 1.1.3 Commonality e.g. AER & related issues Sub retinal and epiretinal approaches both eventually deliver biphasic pulses to the retinal implant to drive the electrodes which in the epiretinal case are in contact with the axons of the ganglion cells. [54], [49], [55], [56], [57], [58]. Medical experiments have indicated that the equivalent impedance for the retina tissue of Retinitis pigmentosa (RP) and Age Related Macular Degeneration (AMD) is about 10kΩ. [53] The default loading for the Virtex 5 FPGA is 50Ω; although this can be altered it is unlikely that a required current to support a charge of 100nC at the electrode tip can be accommodated. On this basis a post processing interface is required as additional driving circuitry for the electrodes of the retinal implant. Address Event Representation (AER) [59], [60], [61], [62] has been chosen as the communication protocol between the sender chip and the receiver chip for two reasons: (1) Identification of each pixels worth of information; by this is meant each individual pixel is identified by its own unique address determined by its positioning on the image to be transmitted. This will enable each AER packet to be tracked and hence routed to its destination electrode driver. (2) Neuromorphic capability in the sense that it is widely perceived as the communication protocol of choice to represent the spikes of biological neural networks and by implication artificial neural networks (ANN) [63-89]. As biological spiking is being represented each AER[90] packet must contain information for pulse length, amplitude, frequency and form. An AER packet as defined in the “Extended Address Event Representation Draft Standard” (http://www.stanford.edu/group/brainsinsilicon/documents/methAER.pdf) has an address with a payload. In other words each specific event has an address 16 of 200
Page 1 and 2: An Address Event Representation (AE
Page 3 and 4: Abstract\Foreword This document pro
Page 5 and 6: Contents An Address Event Represent
Page 7 and 8: --Appendix E FPGA Outputs .........
Page 9 and 10: Figure 48 receiver rtl_16 .........
Page 11 and 12: Chapter 1 Introduction/research aim
Page 13 and 14: foveola (fovea pit) there is a one
Page 15: NB that the photoreceptors of the f
Page 19 and 20: Typically AER is used as a multi se
Page 21 and 22: Real time - innerpulse relationship
Page 23 and 24: the post processing stage of this w
Page 25 and 26: Appendix C: FPGA Sender chip Append
Page 27 and 28: Red (660nm) R / G Red ( 620750nm )
Page 29 and 30: 1 0 1 1 0 0 1 1 0 1 1 1 Table 3 `xo
Page 31 and 32: Adaptive linear combiner w 0 1 Let
Page 33 and 34: is correct (one class) and -1 (the
Page 35 and 36: x2 Linear separation 1.00 0.90 0.80
Page 37 and 38: This is also the Cartesian co-ordin
Page 39 and 40: 2.4 Comparison to Frame Based Repre
Page 41 and 42: Typical GOP structure (Typically an
Page 43 and 44: point is an event occurs for spike
Page 45 and 46: 2.5.1 Files in Appendix A “ycut.m
Page 47 and 48: MPEG-2 setup AER setup Camera Camer
Page 49 and 50: 2.6.2 FPGA representation of epi_re
Page 51 and 52: Chapter 3 Concepts An epiretinal im
Page 53 and 54: AER Transmission lines INPUT image
Page 55 and 56: electrical pulse generated is calle
Page 57 and 58: Figure 25 Retinal colour processing
Page 59 and 60: cells to modulate this luminance pa
Page 61 and 62: L+ M- + - R-G G-R B-Y Y-B Note: L(r
Page 63 and 64: 3.6.2 Retinal operations Light reac
Page 65 and 66: quantified by number of cycles pres
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(Where * is the convolution operato
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T frame C * R * M p Tpacket i.e. Tp
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e relaxed and from (2) the temporal
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one tw o three four five six seven
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3.8.1 Other test images For other b
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Tspike (4ms) Ispike (16ms: interspi
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INDIGO ORANGE YELLOW MAGENTA CYAN B
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4.1 Sender concepts From chapter on
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pixel must equate to 0.02/1024 i.e.
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Clocking hierarchy (32 by 32 image)
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the number of address bits will alt
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Translation report, (3) Map report,
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90 of 200 CLKIN_IN RST_IN pixelcloc
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incorporate colour planes for each
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Chapter 5 Receiver chip The followi
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5.2 Power Analysis Xilinx FPGAs hav
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98 of 200 produce_wire _outputs Ins
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5.5.1 Incoming (short) AER stream T
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Receiver Red plane r1 DAC (4-bit) T
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5.8.2 Electrode size and positionin
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sequence of wiring from the receive
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does this is to inject an equivalen
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6.2.2 Envisaged retinal array This
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a monochrome camera in this space i
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632mW) thus extending battery life
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For the implemented/structural case
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The sender and receiver circuitry p
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Bibliography 1. Woodburn R. Murray
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38. Banks, D.J., P. Degenaar, and C
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74. Freeman, J.A., Skapura, D. M.,
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109. Weiland, J.D., et al. Progress
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141. Indiveri G. Chicca E. Douglas
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172. Singh, P.R., et al. A matched
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206. Stieglitz, T., et al. Developm
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xmixedsource; numberOfFrames = 8; f
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%check {k} =imread (['D:\abc\subima
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%Two for loops the first (outer loo
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%Row break rr6c1=000; rr6c2=000; rr
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--Appendix B FPGA Test setup librar
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stream_blue_pulse_count: out std_lo
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DVI_XCLK_P clock_25MHz, spike_cloc
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use IEEE.STD_LOGIC_UNSIGNED.ALL; --
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--Appendix C FPGA Sender chip libra
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-- else -- resit '1', CLKDV_OUT =>
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FPGA Receiver (structural) chip --A
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FPGA Receiver (structural) chip --E
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FPGA Receiver (structural) chip --r
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FPGA Receiver (structural) chip blu
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FPGA Receiver (structural) chip con
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FPGA Receiver (structural) chip --s
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip --
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FPGA Receiver (structural) chip IO_
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Number with an unused LUT 18 219 8%
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IO Utilization: Number of IOs: 26 N
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The Slice Logic Distribution report
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Router effort level (-rl): Standard
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oming_clock | HOLD | 0.519ns| | 0|
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Part | xc5vlx50tff1136-3 | Process
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Selected Device: 5vlx50tff1136-3 Sl
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used in combination with MAP -timin
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Data Sheet report: ----------------
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“For these implantable devices to
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microstimulator with a 1:4 demultip
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“Medical experiments have estimat
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A Retinomorphic Vision System “In
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“The common language of neuromorp
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