Retinal Prosthesis Dissertation - Student Home Pages

--Appendix B FPGA Test setup
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library XilinxCoreLib;
Library UNISIM;
use UNISIM.vcomponents.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port (USER_CLK: in STD_LOGIC;
DVI_RESET_B: in STD_LOGIC;
--xps_tft_0_TFT_DVI_CLK_N_pin:
STD_LOGIC;
DVI_D0: out STD_LOGIC;
DVI_D1: out STD_LOGIC;
DVI_D2: out STD_LOGIC;
DVI_D3: out STD_LOGIC;
DVI_D4: out STD_LOGIC;
DVI_D5: out STD_LOGIC;
DVI_D6: out STD_LOGIC;
DVI_D7: out STD_LOGIC;
DVI_D8: out STD_LOGIC;
DVI_D9: out STD_LOGIC;
DVI_D10: out STD_LOGIC;
DVI_D11: out STD_LOGIC;
DVI_H: out STD_LOGIC;
DVI_V: out STD_LOGIC;
-- DVI_XCLK_N: out STD_LOGIC;
DVI_DE: out STD_LOGIC;
DVI_XCLK_P: out STD_LOGIC
-- VREF: IN std_logic
);
end top;
out
architecture Structural of top is
--COMPONENT mem_of_pix_1024_f1x is
----generic (width: integer; addr_width: integer);
-- Port (clka: in STD_LOGIC;
-- addra: in STD_LOGIC_VECTOR (9 downto 0);
-- douta: out STD_LOGIC_VECTOR (23 downto 0));
COMPONENT mem_of_aer_stream IS
port (
clka: IN std_logic;
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