Retinal Prosthesis Dissertation - Student Home Pages
Retinal Prosthesis Dissertation - Student Home Pages
Retinal Prosthesis Dissertation - Student Home Pages
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OVERMAPPING of BRAM resources should be ignored if the design is<br />
over-mapped for a non-BRAM resource or if placement fails.<br />
IO Utilization:<br />
Number of bonded IOBs: 23 out of 480 4%<br />
IOB Flip Flops: 4<br />
Place and route report example<br />
Release 11.4 par L.68 (nt)<br />
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.<br />
EECEAYPG11: Thu May 20 14:36:09 2010<br />
par -ise imp_send_1024.ise -w -intstyle ise -ol std -t 1 top_wrapper_map.ncd<br />
top_wrapper.ncd top_wrapper.pcf<br />
Constraints file: top_wrapper.pcf.<br />
"top_wrapper" is an NCD, version 3.2, device xc5vlx50t, package ff1136, speed -3<br />
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv<br />
vv<br />
INFO: Security: 54 - 'xc5vlx50t' is a WebPack part.<br />
----------------------------------------------------------------------<br />
INFO: Par: 465 - The PAR option, "-t" (Starting Placer Cost Table), will be disabled<br />
in the next software release when<br />
used in combination with MAP -timing (Perform Timing-Driven Packing and<br />
Placement) or when run with V5 or newer<br />
architectures. To explore cost tables, please use the MAP option, "-t" (Starting<br />
Placer Cost Table), instead.<br />
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)<br />
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)<br />
INFO: Par: 282 - No user timing constraints were detected or you have set the option<br />
to ignore timing constraints ("par<br />
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically<br />
improve the performance of all<br />
internal clocks in this design. Because there are not defined timing requirements, a<br />
timing score will not be<br />
reported in the PAR report in this mode. The PAR timing summary will list the<br />
performance achieved for each clock.<br />
Note: For the fastest runtime, set the effort level to "std". For best performance,<br />
set the effort level to "high".<br />
Device speed data version: "PRODUCTION 1.66 2009-11-16".<br />
Device Utilization Summary:<br />
Number of BUFGs 4 out of 32 12%<br />
Number of DCM_ADVs 1 out of 12 8%<br />
Number of External IOBs 29 out of 480 6%<br />
Number of LOCed IOBs 0 out of 29 0%<br />
Number of OLOGICs 10 out of 560 1%<br />
Number of RAMB36_EXPs 1 out of 60 1%<br />
Number of Slice Registers 145 out of 28800 1%<br />
Number used as Flip Flops 142<br />
Number used as Latches 3<br />
Number used as LatchThrus 0<br />
Number of Slice LUTS 208 out of 28800 1%<br />
Number of Slice LUT-Flip Flop pairs 217 out of 28800 1%<br />
Overall effort level (-ol): Standard<br />
177 of 200